Asm-X86
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syntax. More code clean-up in unit tests.
* lib/Asm/X86.pm (is_valid_16bit_addr_intel, is_valid_32bit_addr_intel,
is_valid_64bit_addr_intel, is_valid_16bit_addr_att,
is_valid_32bit_addr_att, is_valid_64bit_addr_att): moved common
validation code to private subroutines, saving on duplication
* lib/Asm/X86.pm (is_valid_16bit_addr_att): some expressions have been
widened to allow more matches.
* lib/Asm/X86.pm (is_valid_16bit_addr_att, is_valid_32bit_addr_att,
is_valid_64bit_addr_att): disallow sign characters inside
parentheses (rejected by GNU as).
* lib/Asm/X86.pm (_add_percent, _remove_duplicates, _nopluses): removed
"my sub" and added an underscore to the name to mark the subroutines
as private and still make POD coverage tests skip them.
* lib/Asm/X86.pm (is_reg_intel, is_reg_att, is_reg8_intel, is_reg8_att,
is_reg16_intel, is_reg16_att, is_segreg_intel, is_segreg_att,
is_reg32_intel, is_reg32_att, is_addressable32_intel,
is_addressable32_att, is_r32_in64_intel, is_r32_in64_att,
is_reg64_intel, is_reg64_att, is_reg_mm_intel, is_reg_mm_att,
is_reg_fpu_intel, is_reg_fpu_att, is_reg_opmask_intel,
is_reg_opmask_att, is_instr_intel, is_instr_att): use new private
subroutines to search though the arrays and simplify the code
* lib/Asm/X86.pm (is_reg_intel, is_reg_att, is_reg8_intel, is_reg8_att,
is_reg16_intel, is_reg16_att, is_segreg_intel, is_segreg_att,
is_reg32_intel, is_reg32_att, is_addressable32_intel,
is_addressable32_att, is_r32_in64_intel, is_r32_in64_att,
is_reg64_intel, is_reg64_att, is_reg_mm_intel, is_reg_mm_att,
is_reg_fpu_intel, is_reg_fpu_att, is_reg_opmask_intel,
is_reg_opmask_att, is_instr_intel, is_instr_att): added a pre-check
to check the syntax of the expression before checking the list
* lib/Asm/X86.pm (is_valid_32bit_addr_att, is_valid_64bit_addr_att):
allow '(, reg)' modes
* lib/Asm/X86.pm (add_percent, remove_duplicates, nopluses): made the
subroutines 'my' and removed them from the manual
* lib/Asm/X86.pm: layout fixes for the POD documentation and man page.
Added information that some of the subroutines work best on input
after all preprocessing.
* Makefile.PL: added a variable with the module name
* MANIFEST, KEY: added the GnuPG key used to sign the module
* t/*.t, Makefile.PL: fixed the interpreter line
* t/*.t: significant re-write of tests - using generating procedures,
arrays and loops
* t/zz_addr_mixed.t: partially merged into zz_addr_att.t and
* X86.pm: Updated the instruction list from NASM version 2.10.02.
2012-03-31 Bogdan Drozdowski <bogdro \at\ cpan . org>
* Version 0.13
* X86.pm: Updated the instruction list from NASM version 2.10 and
FASM version 1.69.50. Made is_addressable32_intel,
is_addressable32_att, is_addressable32, is_r32_in64_intel
is_r32_in64_att, is_r32_in64, is_att_suffixed_instr
is_att_suffixed_instr_fpu and add_att_suffix_instr public.
* X86.pm (conv_intel_instr_to_att): corrected removing double percent
character that may be created during the conversion.
* X86.pm (conv_intel_addr_to_att): removing double percent character
that may be created during the conversion.
2012-01-22 Bogdan Drozdowski <bogdro \at\ cpan . org>
* Version 0.12
* X86.pm: Removed duplicates from the instruction and mnemonic list.
Fixed the private subroutine add_att_suffix_instr (some AT&T
instructions were not generated). Added one new register, CR8
(available only in 64-bit mode).
* X86.pm, README: Bump the year in the copyright notices.
lib/Asm/X86.pm view on Meta::CPAN
@instr
These contain all register and instruction mnemonic names as lower-case strings.
The "_intel" and "_att" suffixes mean the Intel and AT&T syntaxes, respectively.
No suffix means either Intel or AT&T.
=head1 DATA
=cut
# =head2 _add_percent
#
# PRIVATE SUBROUTINE.
# Add a percent character ('%') in front of each element in the array given as a parameter.
# Returns the new array.
#
# =cut
sub _add_percent(@) {
my @result = ();
foreach (@_) {
push @result, "%$_";
}
return @result;
}
# =head2 _remove_duplicates
#
lib/Asm/X86.pm view on Meta::CPAN
'r12b', 'r13b', 'r14b', 'r15b', 'sil', 'dil', 'spl', 'bpl',
'ah', 'bh', 'ch', 'dh'
);
=head2 @regs8_att
A list of 8-bit registers (as strings) in AT&T syntax.
=cut
our @regs8_att = _add_percent @regs8_intel;
=head2 @segregs_intel
A list of segment registers (as strings) in Intel syntax.
=cut
our @segregs_intel = ( 'cs', 'ds', 'es', 'fs', 'gs', 'ss' );
=head2 @segregs_att
A list of segment registers (as strings) in AT&T syntax.
=cut
our @segregs_att = _add_percent @segregs_intel;
=head2 @regs16_intel
A list of 16-bit registers (as strings), including the segment registers, in Intel syntax.
=cut
our @regs16_intel = (
'ax', 'bx', 'cx', 'dx', 'r8w', 'r9w', 'r10w', 'r11w',
'r12w', 'r13w', 'r14w', 'r15w', 'si', 'di', 'sp', 'bp',
@segregs_intel
);
=head2 @regs16_att
A list of 16-bit registers (as strings), including the segment registers, in AT&T syntax.
=cut
our @regs16_att = _add_percent @regs16_intel;
my @addressable32 = ('eax', 'ebx', 'ecx', 'edx', 'esi', 'edi', 'esp', 'ebp');
my @addressable32_att = _add_percent @addressable32;
my @r32_in64 = (
'r8d', 'r8l', 'r9d', 'r9l', 'r10d', 'r10l', 'r11d', 'r11l',
'r12d', 'r12l', 'r13d', 'r13l', 'r14d', 'r14l', 'r15d', 'r15l',
);
my @r32_in64_att = _add_percent @r32_in64;
=head2 @regs32_intel
A list of 32-bit registers (as strings) in Intel syntax.
=cut
our @regs32_intel = (
@addressable32,
'cr0', 'cr2', 'cr3', 'cr4', 'cr8',
'dr0', 'dr1', 'dr2', 'dr3', 'dr6', 'dr7',
@r32_in64
);
=head2 @regs32_att
A list of 32-bit registers (as strings) in AT&T syntax.
=cut
our @regs32_att = _add_percent @regs32_intel;
=head2 @regs_fpu_intel
A list of FPU registers (as strings) in Intel syntax.
=cut
our @regs_fpu_intel = ('st0', 'st1', 'st2', 'st3', 'st4', 'st5', 'st6', 'st7');
=head2 @regs_fpu_att
A list of FPU registers (as strings) in AT&T syntax.
=cut
our @regs_fpu_att = _add_percent @regs_fpu_intel;
=head2 @regs64_intel
A list of 64-bit registers (as strings) in Intel syntax.
=cut
our @regs64_intel = (
'rax', 'rbx', 'rcx', 'rdx', 'r8', 'r9', 'r10', 'r11',
'r12', 'r13', 'r14', 'r15', 'rsi', 'rdi', 'rsp', 'rbp', 'rip'
);
=head2 @regs64_att
A list of 64-bit registers (as strings) in AT&T syntax.
=cut
our @regs64_att = _add_percent @regs64_intel;
=head2 @regs_mm_intel
A list of multimedia (MMX/3DNow!/SSEn) registers (as strings) in Intel syntax.
=cut
our @regs_mm_intel = (
'mm0', 'mm1', 'mm2', 'mm3', 'mm4', 'mm5', 'mm6', 'mm7',
'xmm0', 'xmm1', 'xmm2', 'xmm3', 'xmm4', 'xmm5', 'xmm6', 'xmm7',
lib/Asm/X86.pm view on Meta::CPAN
'zmm24', 'zmm25', 'zmm26', 'zmm27', 'zmm28', 'zmm29', 'zmm30', 'zmm31'
);
=head2 @regs_mm_att
A list of multimedia (MMX/3DNow!/SSEn) registers (as strings) in AT&T syntax.
=cut
our @regs_mm_att = _add_percent @regs_mm_intel;
=head2 @regs_opmask_intel
A list of opmask registers (as strings) in Intel syntax.
=cut
our @regs_opmask_intel = ('k0', 'k1', 'k2', 'k3', 'k4', 'k5', 'k6', 'k7');
=head2 @regs_opmask_att
A list of opmask registers (as strings) in AT&T syntax.
=cut
our @regs_opmask_att = _add_percent @regs_opmask_intel;
=head2 @regs_bound_intel
A list of bound registers (as strings) in Intel syntax.
=cut
our @regs_bound_intel = ('bnd0', 'bnd1', 'bnd2', 'bnd3');
=head2 @regs_bound_att
A list of bound registers (as strings) in AT&T syntax.
=cut
our @regs_bound_att = _add_percent @regs_bound_intel;
=head2 @regs_intel
A list of all x86 registers (as strings) in Intel syntax.
=cut
our @regs_intel = ( @regs8_intel, @regs16_intel, @regs32_intel,
@regs64_intel, @regs_mm_intel, @regs_fpu_intel,
@regs_opmask_intel, @regs_bound_intel );
lib/Asm/X86.pm view on Meta::CPAN
$a2 = _change_to_intel_addr_if_applicable ($a2);
# (ATTENTION: operand order will be changed later)
$par = "\t$a1\t$a2\n";
}
}
# (removing dollar chars)
$par =~ s/\$//go;
# (removing percent chars)
$par =~ s/%//go;
# (removing asterisk chars)
$par =~ s/\*//go;
# (changing memory references):
$par = conv_att_addr_to_intel $par;
# (changing "st[N]" to "stN")
$par =~ s/(\s)st\[(\d)\]/$1 st$2/go;
# (changing "st" to "st0")
lib/Asm/X86.pm view on Meta::CPAN
$par =~ s/^\s*(jmp|call)\s+([dp]word|word|near|far|short)?\s*([\w\*\+\-\s]+)/\t$1\t$3/io;
$par =~ s/^\s*(jmp|call)\s+([^:]+)\s*:\s*([^:]+)/\tl$1\t$2, $3/io;
$par =~ s/^\s*retf\s+(.*)$/\tlret\t$1/io;
# (changing memory references):
$par = conv_intel_addr_to_att $par;
# (changing "stN" to "st(N)")
$par =~ s/\bst(\d)\b/\%st($1)/go;
# (adding percent chars)
foreach my $r (@regs_intel) {
$par =~ s/\b$r\b/\%$r/gi;
}
foreach my $r (@regs_intel) {
$par =~ s/\%\%$r\b/\%$r/gi;
}
# (REP**: adding the end of line char)
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