Alien-libsecp256k1

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libsecp256k1/include/secp256k1_extrakeys.h  view on Meta::CPAN

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    const unsigned char *tweak32
) SECP256K1_ARG_NONNULL(1) SECP256K1_ARG_NONNULL(2) SECP256K1_ARG_NONNULL(3) SECP256K1_ARG_NONNULL(4);
 
/** Checks that a tweaked pubkey is the result of calling
 *  secp256k1_xonly_pubkey_tweak_add with internal_pubkey and tweak32.
 *
 *  The tweaked pubkey is represented by its 32-byte x-only serialization and
 *  its pk_parity, which can both be obtained by converting the result of
 *  tweak_add to a secp256k1_xonly_pubkey.
 *
 *  Note that this alone does _not_ verify that the tweaked pubkey is a
 *  commitment. If the tweak is not chosen in a specific way, the tweaked pubkey
 *  can easily be the result of a different internal_pubkey and tweak.
 *
 *  Returns: 0 if the arguments are invalid or the tweaked pubkey is not the
 *           result of tweaking the internal_pubkey with tweak32. 1 otherwise.
 *  Args:            ctx: pointer to a context object.
 *  In: tweaked_pubkey32: pointer to a serialized xonly_pubkey.
 *     tweaked_pk_parity: the parity of the tweaked pubkey (whose serialization
 *                        is passed in as tweaked_pubkey32). This must match the
 *                        pk_parity value that is returned when calling

libsecp256k1/include/secp256k1_schnorrsig.h  view on Meta::CPAN

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#define SECP256K1_SCHNORRSIG_EXTRAPARAMS_MAGIC { 0xda, 0x6f, 0xb3, 0x8c }
#define SECP256K1_SCHNORRSIG_EXTRAPARAMS_INIT {\
    SECP256K1_SCHNORRSIG_EXTRAPARAMS_MAGIC,\
    NULL,\
    NULL\
}
 
/** Create a Schnorr signature.
 *
 *  Does _not_ strictly follow BIP-340 because it does not verify the resulting
 *  signature. Instead, you can manually use secp256k1_schnorrsig_verify and
 *  abort if it fails.
 *
 *  This function only signs 32-byte messages. If you have messages of a
 *  different size (or the same size but without a context-specific tag
 *  prefix), it is recommended to create a 32-byte message hash with
 *  secp256k1_tagged_sha256 and then sign the hash. Tagged hashing allows
 *  providing an context-specific tag for domain separation. This prevents
 *  signatures from being valid in multiple contexts by accident.
 *

libsecp256k1/src/asm/field_10x26_arm.s  view on Meta::CPAN

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.syntax unified
@ eabi attributes - see readelf -A
.eabi_attribute 24, 1 @ Tag_ABI_align_needed = 8-byte
.eabi_attribute 25, 1 @ Tag_ABI_align_preserved = 8-byte, except leaf SP
.text
 
@ Field constants
.set field_R0, 0x3d10
.set field_R1, 0x400
.set field_not_M, 0xfc000000    @ ~M = ~0x3ffffff
 
.align  2
.global secp256k1_fe_mul_inner
.type   secp256k1_fe_mul_inner, %function
.hidden secp256k1_fe_mul_inner
@ Arguments:
@  r0  r      Restrict: can overlap with a, not with b
@  r1  a
@  r2  b
@ Stack (total 4+10*4 = 44)

libsecp256k1/src/asm/field_10x26_arm.s  view on Meta::CPAN

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ldr     r8, [r2, #1*4]                  @ b[1]
umlal   r9, r10, r7, r14                @ d' += a[8] * b[2]
ldr     r0, [r1, #9*4]                  @ a[9]
umlal   r5, r6, r7, r8                  @ d += a[8] * b[1]
ldr     r14, [r2, #0*4]                 @ b[0]
umlal   r9, r10, r0, r8                 @ d' += a[9] * b[1]
ldr     r7, [r1, #0*4]                  @ a[0]
umlal   r5, r6, r0, r14                 @ d += a[9] * b[0]
@ r7,r14 used in B
 
bic     r0, r5, field_not_M             @ t9 = d & M
str     r0, [sp, #4 + 4*9]
mov     r5, r5, lsr #26                 @ d >>= 26
orr     r5, r5, r6, asl #6
mov     r6, r6, lsr #26
 
/* B */
umull   r3, r4, r7, r14                 @ c = a[0] * b[0]
adds    r5, r5, r9                      @ d += d'
adc     r6, r6, r10
 
bic     r0, r5, field_not_M             @ u0 = d & M
mov     r5, r5, lsr #26                 @ d >>= 26
orr     r5, r5, r6, asl #6
mov     r6, r6, lsr #26
movw    r14, field_R0                   @ c += u0 * R0
umlal   r3, r4, r0, r14
 
bic     r14, r3, field_not_M            @ t0 = c & M
str     r14, [sp, #4 + 0*4]
mov     r3, r3, lsr #26                 @ c >>= 26
orr     r3, r3, r4, asl #6
mov     r4, r4, lsr #26
mov     r14, field_R1                   @ c += u0 * R1
umlal   r3, r4, r0, r14
 
/* C - interleaved with D */
ldr     r7, [r1, #0*4]                  @ a[0]
ldr     r8, [r2, #2*4]                  @ b[2]

libsecp256k1/src/asm/field_10x26_arm.s  view on Meta::CPAN

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ldr     r7, [r1, #8*4]                  @ a[8]
umlal   r5, r6, r0, r8                  @ d += a[7] * b[4]
ldr     r14, [r2, #3*4]                 @ b[3]
umlal   r9, r10, r7, r8                 @ d' += a[8] * b[4]
ldr     r0, [r1, #9*4]                  @ a[9]
umlal   r5, r6, r7, r14                 @ d += a[8] * b[3]
ldr     r8, [r2, #2*4]                  @ b[2]
umlal   r9, r10, r0, r14                @ d' += a[9] * b[3]
umlal   r5, r6, r0, r8                  @ d += a[9] * b[2]
 
bic     r0, r5, field_not_M             @ u1 = d & M
mov     r5, r5, lsr #26                 @ d >>= 26
orr     r5, r5, r6, asl #6
mov     r6, r6, lsr #26
movw    r14, field_R0                   @ c += u1 * R0
umlal   r3, r4, r0, r14
 
bic     r14, r3, field_not_M            @ t1 = c & M
str     r14, [sp, #4 + 1*4]
mov     r3, r3, lsr #26                 @ c >>= 26
orr     r3, r3, r4, asl #6
mov     r4, r4, lsr #26
mov     r14, field_R1                   @ c += u1 * R1
umlal   r3, r4, r0, r14
 
/* D */
adds    r3, r3, r11                     @ c += c'
adc     r4, r4, r12
adds    r5, r5, r9                      @ d += d'
adc     r6, r6, r10
 
bic     r0, r5, field_not_M             @ u2 = d & M
mov     r5, r5, lsr #26                 @ d >>= 26
orr     r5, r5, r6, asl #6
mov     r6, r6, lsr #26
movw    r14, field_R0                   @ c += u2 * R0
umlal   r3, r4, r0, r14
 
bic     r14, r3, field_not_M            @ t2 = c & M
str     r14, [sp, #4 + 2*4]
mov     r3, r3, lsr #26                 @ c >>= 26
orr     r3, r3, r4, asl #6
mov     r4, r4, lsr #26
mov     r14, field_R1                   @ c += u2 * R1
umlal   r3, r4, r0, r14
 
/* E - interleaved with F */
ldr     r7, [r1, #0*4]                  @ a[0]
ldr     r8, [r2, #4*4]                  @ b[4]

libsecp256k1/src/asm/field_10x26_arm.s  view on Meta::CPAN

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umlal   r5, r6, r7, r8                  @ d += a[7] * b[6]
ldr     r7, [r1, #8*4]                  @ a[8]
umlal   r9, r10, r7, r8                 @ d' += a[8] * b[6]
ldr     r8, [r2, #5*4]                  @ b[5]
umlal   r5, r6, r7, r8                  @ d += a[8] * b[5]
ldr     r7, [r1, #9*4]                  @ a[9]
umlal   r9, r10, r7, r8                 @ d' += a[9] * b[5]
ldr     r8, [r2, #4*4]                  @ b[4]
umlal   r5, r6, r7, r8                  @ d += a[9] * b[4]
 
bic     r0, r5, field_not_M             @ u3 = d & M
mov     r5, r5, lsr #26                 @ d >>= 26
orr     r5, r5, r6, asl #6
mov     r6, r6, lsr #26
movw    r14, field_R0                   @ c += u3 * R0
umlal   r3, r4, r0, r14
 
bic     r14, r3, field_not_M            @ t3 = c & M
str     r14, [sp, #4 + 3*4]
mov     r3, r3, lsr #26                 @ c >>= 26
orr     r3, r3, r4, asl #6
mov     r4, r4, lsr #26
mov     r14, field_R1                   @ c += u3 * R1
umlal   r3, r4, r0, r14
 
/* F */
adds    r3, r3, r11                     @ c += c'
adc     r4, r4, r12
adds    r5, r5, r9                      @ d += d'
adc     r6, r6, r10
 
bic     r0, r5, field_not_M             @ u4 = d & M
mov     r5, r5, lsr #26                 @ d >>= 26
orr     r5, r5, r6, asl #6
mov     r6, r6, lsr #26
movw    r14, field_R0                   @ c += u4 * R0
umlal   r3, r4, r0, r14
 
bic     r14, r3, field_not_M            @ t4 = c & M
str     r14, [sp, #4 + 4*4]
mov     r3, r3, lsr #26                 @ c >>= 26
orr     r3, r3, r4, asl #6
mov     r4, r4, lsr #26
mov     r14, field_R1                   @ c += u4 * R1
umlal   r3, r4, r0, r14
 
/* G - interleaved with H */
ldr     r7, [r1, #0*4]                  @ a[0]
ldr     r8, [r2, #6*4]                  @ b[6]

libsecp256k1/src/asm/field_10x26_arm.s  view on Meta::CPAN

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ldr     r7, [r1, #8*4]                  @ a[8]
umlal   r5, r6, r0, r8                  @ d += a[7] * b[8]
ldr     r14, [r2, #7*4]                 @ b[7]
umlal   r9, r10, r7, r8                 @ d' += a[8] * b[8]
ldr     r0, [r1, #9*4]                  @ a[9]
umlal   r5, r6, r7, r14                 @ d += a[8] * b[7]
ldr     r8, [r2, #6*4]                  @ b[6]
umlal   r9, r10, r0, r14                @ d' += a[9] * b[7]
umlal   r5, r6, r0, r8                  @ d += a[9] * b[6]
 
bic     r0, r5, field_not_M             @ u5 = d & M
mov     r5, r5, lsr #26                 @ d >>= 26
orr     r5, r5, r6, asl #6
mov     r6, r6, lsr #26
movw    r14, field_R0                   @ c += u5 * R0
umlal   r3, r4, r0, r14
 
bic     r14, r3, field_not_M            @ t5 = c & M
str     r14, [sp, #4 + 5*4]
mov     r3, r3, lsr #26                 @ c >>= 26
orr     r3, r3, r4, asl #6
mov     r4, r4, lsr #26
mov     r14, field_R1                   @ c += u5 * R1
umlal   r3, r4, r0, r14
 
/* H */
adds    r3, r3, r11                     @ c += c'
adc     r4, r4, r12
adds    r5, r5, r9                      @ d += d'
adc     r6, r6, r10
 
bic     r0, r5, field_not_M             @ u6 = d & M
mov     r5, r5, lsr #26                 @ d >>= 26
orr     r5, r5, r6, asl #6
mov     r6, r6, lsr #26
movw    r14, field_R0                   @ c += u6 * R0
umlal   r3, r4, r0, r14
 
bic     r14, r3, field_not_M            @ t6 = c & M
str     r14, [sp, #4 + 6*4]
mov     r3, r3, lsr #26                 @ c >>= 26
orr     r3, r3, r4, asl #6
mov     r4, r4, lsr #26
mov     r14, field_R1                   @ c += u6 * R1
umlal   r3, r4, r0, r14
 
/* I - interleaved with J */
ldr     r8, [r2, #8*4]                  @ b[8]
ldr     r7, [r1, #0*4]                  @ a[0]

libsecp256k1/src/asm/field_10x26_arm.s  view on Meta::CPAN

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ldr     r7, [r1, #8*4]                  @ a[8]
umlal   r3, r4, r0, r8                  @ c += a[7] * b[0]
ldr     r14, [r2, #9*4]                 @ b[9]
umlal   r11, r12, r7, r8                @ c' += a[8] * b[0]
ldr     r0, [r1, #9*4]                  @ a[9]
umlal   r5, r6, r7, r14                 @ d += a[8] * b[9]
ldr     r8, [r2, #8*4]                  @ b[8]
umull   r9, r10, r0, r14                @ d' = a[9] * b[9]
umlal   r5, r6, r0, r8                  @ d += a[9] * b[8]
 
bic     r0, r5, field_not_M             @ u7 = d & M
mov     r5, r5, lsr #26                 @ d >>= 26
orr     r5, r5, r6, asl #6
mov     r6, r6, lsr #26
movw    r14, field_R0                   @ c += u7 * R0
umlal   r3, r4, r0, r14
 
bic     r14, r3, field_not_M            @ t7 = c & M
str     r14, [sp, #4 + 7*4]
mov     r3, r3, lsr #26                 @ c >>= 26
orr     r3, r3, r4, asl #6
mov     r4, r4, lsr #26
mov     r14, field_R1                   @ c += u7 * R1
umlal   r3, r4, r0, r14
 
/* J */
adds    r3, r3, r11                     @ c += c'
adc     r4, r4, r12
adds    r5, r5, r9                      @ d += d'
adc     r6, r6, r10
 
bic     r0, r5, field_not_M             @ u8 = d & M
str     r0, [sp, #4 + 8*4]
mov     r5, r5, lsr #26                 @ d >>= 26
orr     r5, r5, r6, asl #6
mov     r6, r6, lsr #26
movw    r14, field_R0                   @ c += u8 * R0
umlal   r3, r4, r0, r14
 
/******************************************
 * compute and write back result
 ******************************************

libsecp256k1/src/asm/field_10x26_arm.s  view on Meta::CPAN

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    r1,r2,r10,r14 scratch
 
Note: do not read from a[] after here, it may overlap with r[]
*/
ldr     r0, [sp, #0]
add     r1, sp, #4 + 3*4                @ r[3..7] = t3..7, r11=u8, r12=t9
ldmia   r1, {r2,r7,r8,r9,r10,r11,r12}
add     r1, r0, #3*4
stmia   r1, {r2,r7,r8,r9,r10}
 
bic     r2, r3, field_not_M             @ r[8] = c & M
str     r2, [r0, #8*4]
mov     r3, r3, lsr #26                 @ c >>= 26
orr     r3, r3, r4, asl #6
mov     r4, r4, lsr #26
mov     r14, field_R1                   @ c += u8 * R1
umlal   r3, r4, r11, r14
movw    r14, field_R0                   @ c += d * R0
umlal   r3, r4, r5, r14
adds    r3, r3, r12                     @ c += t9
adc     r4, r4, #0

libsecp256k1/src/asm/field_10x26_arm.s  view on Meta::CPAN

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mov     r4, r4, lsr #22
movw    r14, field_R1 << 4                @ c += d * (R1 << 4)
umlal   r3, r4, r5, r14
 
movw    r14, field_R0 >> 4                @ d = c * (R0 >> 4) + t0 (64x64 multiply+add)
umull   r5, r6, r3, r14                 @ d = c.lo * (R0 >> 4)
adds    r5, r5, r7                      @ d.lo += t0
mla     r6, r14, r4, r6                 @ d.hi += c.hi * (R0 >> 4)
adc     r6, r6, 0                       @ d.hi += carry
 
bic     r2, r5, field_not_M             @ r[0] = d & M
str     r2, [r0, #0*4]
 
mov     r5, r5, lsr #26                 @ d >>= 26
orr     r5, r5, r6, asl #6
mov     r6, r6, lsr #26
 
movw    r14, field_R1 >> 4                @ d += c * (R1 >> 4) + t1 (64x64 multiply+add)
umull   r1, r2, r3, r14                 @ tmp = c.lo * (R1 >> 4)
adds    r5, r5, r8                      @ d.lo += t1
adc     r6, r6, #0                      @ d.hi += carry
adds    r5, r5, r1                      @ d.lo += tmp.lo
mla     r2, r14, r4, r2                 @ tmp.hi += c.hi * (R1 >> 4)
adc     r6, r6, r2                      @ d.hi += carry + tmp.hi
 
bic     r2, r5, field_not_M             @ r[1] = d & M
str     r2, [r0, #1*4]
mov     r5, r5, lsr #26                 @ d >>= 26 (ignore hi)
orr     r5, r5, r6, asl #6
 
add     r5, r5, r9                      @ d += t2
str     r5, [r0, #2*4]                  @ r[2] = d
 
add     sp, sp, #48
ldmfd   sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc}
.size   secp256k1_fe_mul_inner, .-secp256k1_fe_mul_inner

libsecp256k1/src/asm/field_10x26_arm.s  view on Meta::CPAN

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mov     r0, r0, asl #1
ldr     r7, [r1, #4*4]                  @ a[4]*2
umlal   r9, r10, r0, r14                @ d' += a[3]*2 * a[7]
ldr     r14, [r1, #5*4]                 @ a[5]
mov     r7, r7, asl #1
umlal   r5, r6, r0, r8                  @ d += a[3]*2 * a[6]
umlal   r9, r10, r7, r8                 @ d' += a[4]*2 * a[6]
umlal   r5, r6, r7, r14                 @ d += a[4]*2 * a[5]
umlal   r9, r10, r14, r14               @ d' += a[5] * a[5]
 
bic     r0, r5, field_not_M             @ t9 = d & M
str     r0, [sp, #4 + 9*4]
mov     r5, r5, lsr #26                 @ d >>= 26
orr     r5, r5, r6, asl #6
mov     r6, r6, lsr #26
 
/* B */
adds    r5, r5, r9                      @ d += d'
adc     r6, r6, r10
 
bic     r0, r5, field_not_M             @ u0 = d & M
mov     r5, r5, lsr #26                 @ d >>= 26
orr     r5, r5, r6, asl #6
mov     r6, r6, lsr #26
movw    r14, field_R0                   @ c += u0 * R0
umlal   r3, r4, r0, r14
bic     r14, r3, field_not_M            @ t0 = c & M
str     r14, [sp, #4 + 0*4]
mov     r3, r3, lsr #26                 @ c >>= 26
orr     r3, r3, r4, asl #6
mov     r4, r4, lsr #26
mov     r14, field_R1                   @ c += u0 * R1
umlal   r3, r4, r0, r14
 
/* C interleaved with D */
ldr     r0, [r1, #0*4]                  @ a[0]*2
ldr     r14, [r1, #1*4]                 @ a[1]

libsecp256k1/src/asm/field_10x26_arm.s  view on Meta::CPAN

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mov     r7, r7, asl #1
ldr     r0, [r1, #5*4]                  @ a[5]*2
umlal   r9, r10, r7, r8                 @ d' += a[4]*2 * a[8]
ldr     r8, [r1, #6*4]                  @ a[6]
mov     r0, r0, asl #1
umlal   r5, r6, r7, r14                 @ d += a[4]*2 * a[7]
umlal   r9, r10, r0, r14                @ d' += a[5]*2 * a[7]
umlal   r5, r6, r0, r8                  @ d += a[5]*2 * a[6]
umlal   r9, r10, r8, r8                 @ d' += a[6] * a[6]
 
bic     r0, r5, field_not_M             @ u1 = d & M
mov     r5, r5, lsr #26                 @ d >>= 26
orr     r5, r5, r6, asl #6
mov     r6, r6, lsr #26
movw    r14, field_R0                   @ c += u1 * R0
umlal   r3, r4, r0, r14
bic     r14, r3, field_not_M            @ t1 = c & M
str     r14, [sp, #4 + 1*4]
mov     r3, r3, lsr #26                 @ c >>= 26
orr     r3, r3, r4, asl #6
mov     r4, r4, lsr #26
mov     r14, field_R1                   @ c += u1 * R1
umlal   r3, r4, r0, r14
 
/* D */
adds    r3, r3, r11                     @ c += c'
adc     r4, r4, r12
adds    r5, r5, r9                      @ d += d'
adc     r6, r6, r10
 
bic     r0, r5, field_not_M             @ u2 = d & M
mov     r5, r5, lsr #26                 @ d >>= 26
orr     r5, r5, r6, asl #6
mov     r6, r6, lsr #26
movw    r14, field_R0                   @ c += u2 * R0
umlal   r3, r4, r0, r14
bic     r14, r3, field_not_M            @ t2 = c & M
str     r14, [sp, #4 + 2*4]
mov     r3, r3, lsr #26                 @ c >>= 26
orr     r3, r3, r4, asl #6
mov     r4, r4, lsr #26
mov     r14, field_R1                   @ c += u2 * R1
umlal   r3, r4, r0, r14
 
/* E interleaved with F */
ldr     r7, [r1, #0*4]                  @ a[0]*2
ldr     r0, [r1, #1*4]                  @ a[1]*2

libsecp256k1/src/asm/field_10x26_arm.s  view on Meta::CPAN

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umlal   r5, r6, r2, r8                  @ d += a[4]*2 * a[9]
ldr     r7, [r1, #6*4]                  @ a[6]*2
umull   r9, r10, r0, r8                 @ d' = a[5]*2 * a[9]
mov     r7, r7, asl #1
ldr     r8, [r1, #7*4]                  @ a[7]
umlal   r5, r6, r0, r14                 @ d += a[5]*2 * a[8]
umlal   r9, r10, r7, r14                @ d' += a[6]*2 * a[8]
umlal   r5, r6, r7, r8                  @ d += a[6]*2 * a[7]
umlal   r9, r10, r8, r8                 @ d' += a[7] * a[7]
 
bic     r0, r5, field_not_M             @ u3 = d & M
mov     r5, r5, lsr #26                 @ d >>= 26
orr     r5, r5, r6, asl #6
mov     r6, r6, lsr #26
movw    r14, field_R0                   @ c += u3 * R0
umlal   r3, r4, r0, r14
bic     r14, r3, field_not_M            @ t3 = c & M
str     r14, [sp, #4 + 3*4]
mov     r3, r3, lsr #26                 @ c >>= 26
orr     r3, r3, r4, asl #6
mov     r4, r4, lsr #26
mov     r14, field_R1                   @ c += u3 * R1
umlal   r3, r4, r0, r14
 
/* F */
adds    r3, r3, r11                     @ c += c'
adc     r4, r4, r12
adds    r5, r5, r9                      @ d += d'
adc     r6, r6, r10
 
bic     r0, r5, field_not_M             @ u4 = d & M
mov     r5, r5, lsr #26                 @ d >>= 26
orr     r5, r5, r6, asl #6
mov     r6, r6, lsr #26
movw    r14, field_R0                   @ c += u4 * R0
umlal   r3, r4, r0, r14
bic     r14, r3, field_not_M            @ t4 = c & M
str     r14, [sp, #4 + 4*4]
mov     r3, r3, lsr #26                 @ c >>= 26
orr     r3, r3, r4, asl #6
mov     r4, r4, lsr #26
mov     r14, field_R1                   @ c += u4 * R1
umlal   r3, r4, r0, r14
 
/* G interleaved with H */
ldr     r7, [r1, #0*4]                  @ a[0]*2
ldr     r0, [r1, #1*4]                  @ a[1]*2

libsecp256k1/src/asm/field_10x26_arm.s  view on Meta::CPAN

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umlal   r3, r4, r7, r8                  @ c += a[2]*2 * a[3]
ldr     r7, [r1, #7*4]                  @ a[7]*2
umlal   r11, r12, r8, r8                @ c' += a[3] * a[3]
mov     r7, r7, asl #1
ldr     r8, [r1, #8*4]                  @ a[8]
umlal   r5, r6, r0, r14                 @ d += a[6]*2 * a[9]
umull   r9, r10, r7, r14                @ d' = a[7]*2 * a[9]
umlal   r5, r6, r7, r8                  @ d += a[7]*2 * a[8]
umlal   r9, r10, r8, r8                 @ d' += a[8] * a[8]
 
bic     r0, r5, field_not_M             @ u5 = d & M
mov     r5, r5, lsr #26                 @ d >>= 26
orr     r5, r5, r6, asl #6
mov     r6, r6, lsr #26
movw    r14, field_R0                   @ c += u5 * R0
umlal   r3, r4, r0, r14
bic     r14, r3, field_not_M            @ t5 = c & M
str     r14, [sp, #4 + 5*4]
mov     r3, r3, lsr #26                 @ c >>= 26
orr     r3, r3, r4, asl #6
mov     r4, r4, lsr #26
mov     r14, field_R1                   @ c += u5 * R1
umlal   r3, r4, r0, r14
 
/* H */
adds    r3, r3, r11                     @ c += c'
adc     r4, r4, r12
adds    r5, r5, r9                      @ d += d'
adc     r6, r6, r10
 
bic     r0, r5, field_not_M             @ u6 = d & M
mov     r5, r5, lsr #26                 @ d >>= 26
orr     r5, r5, r6, asl #6
mov     r6, r6, lsr #26
movw    r14, field_R0                   @ c += u6 * R0
umlal   r3, r4, r0, r14
bic     r14, r3, field_not_M            @ t6 = c & M
str     r14, [sp, #4 + 6*4]
mov     r3, r3, lsr #26                 @ c >>= 26
orr     r3, r3, r4, asl #6
mov     r4, r4, lsr #26
mov     r14, field_R1                   @ c += u6 * R1
umlal   r3, r4, r0, r14
 
/* I interleaved with J */
ldr     r7, [r1, #0*4]                  @ a[0]*2
ldr     r0, [r1, #1*4]                  @ a[1]*2

libsecp256k1/src/asm/field_10x26_arm.s  view on Meta::CPAN

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mov     r0, r0, asl #1
umlal   r3, r4, r7, r8                  @ c += a[2]*2 * a[5]
mov     r2, r2, asl #1                  @ a[8]*2
umlal   r11, r12, r0, r8                @ c' += a[3]*2 * a[5]
umlal   r3, r4, r0, r14                 @ c += a[3]*2 * a[4]
umlal   r11, r12, r14, r14              @ c' += a[4] * a[4]
ldr     r8, [r1, #9*4]                  @ a[9]
umlal   r5, r6, r2, r8                  @ d += a[8]*2 * a[9]
@ r8 will be used in J
 
bic     r0, r5, field_not_M             @ u7 = d & M
mov     r5, r5, lsr #26                 @ d >>= 26
orr     r5, r5, r6, asl #6
mov     r6, r6, lsr #26
movw    r14, field_R0                   @ c += u7 * R0
umlal   r3, r4, r0, r14
bic     r14, r3, field_not_M            @ t7 = c & M
str     r14, [sp, #4 + 7*4]
mov     r3, r3, lsr #26                 @ c >>= 26
orr     r3, r3, r4, asl #6
mov     r4, r4, lsr #26
mov     r14, field_R1                   @ c += u7 * R1
umlal   r3, r4, r0, r14
 
/* J */
adds    r3, r3, r11                     @ c += c'
adc     r4, r4, r12
umlal   r5, r6, r8, r8                  @ d += a[9] * a[9]
 
bic     r0, r5, field_not_M             @ u8 = d & M
str     r0, [sp, #4 + 8*4]
mov     r5, r5, lsr #26                 @ d >>= 26
orr     r5, r5, r6, asl #6
mov     r6, r6, lsr #26
movw    r14, field_R0                   @ c += u8 * R0
umlal   r3, r4, r0, r14
 
/******************************************
 * compute and write back result
 ******************************************

libsecp256k1/src/asm/field_10x26_arm.s  view on Meta::CPAN

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    r1,r2,r10,r14 scratch
 
Note: do not read from a[] after here, it may overlap with r[]
*/
ldr     r0, [sp, #0]
add     r1, sp, #4 + 3*4                @ r[3..7] = t3..7, r11=u8, r12=t9
ldmia   r1, {r2,r7,r8,r9,r10,r11,r12}
add     r1, r0, #3*4
stmia   r1, {r2,r7,r8,r9,r10}
 
bic     r2, r3, field_not_M             @ r[8] = c & M
str     r2, [r0, #8*4]
mov     r3, r3, lsr #26                 @ c >>= 26
orr     r3, r3, r4, asl #6
mov     r4, r4, lsr #26
mov     r14, field_R1                   @ c += u8 * R1
umlal   r3, r4, r11, r14
movw    r14, field_R0                   @ c += d * R0
umlal   r3, r4, r5, r14
adds    r3, r3, r12                     @ c += t9
adc     r4, r4, #0

libsecp256k1/src/asm/field_10x26_arm.s  view on Meta::CPAN

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mov     r4, r4, lsr #22
movw    r14, field_R1 << 4                @ c += d * (R1 << 4)
umlal   r3, r4, r5, r14
 
movw    r14, field_R0 >> 4                @ d = c * (R0 >> 4) + t0 (64x64 multiply+add)
umull   r5, r6, r3, r14                 @ d = c.lo * (R0 >> 4)
adds    r5, r5, r7                      @ d.lo += t0
mla     r6, r14, r4, r6                 @ d.hi += c.hi * (R0 >> 4)
adc     r6, r6, 0                       @ d.hi += carry
 
bic     r2, r5, field_not_M             @ r[0] = d & M
str     r2, [r0, #0*4]
 
mov     r5, r5, lsr #26                 @ d >>= 26
orr     r5, r5, r6, asl #6
mov     r6, r6, lsr #26
 
movw    r14, field_R1 >> 4                @ d += c * (R1 >> 4) + t1 (64x64 multiply+add)
umull   r1, r2, r3, r14                 @ tmp = c.lo * (R1 >> 4)
adds    r5, r5, r8                      @ d.lo += t1
adc     r6, r6, #0                      @ d.hi += carry
adds    r5, r5, r1                      @ d.lo += tmp.lo
mla     r2, r14, r4, r2                 @ tmp.hi += c.hi * (R1 >> 4)
adc     r6, r6, r2                      @ d.hi += carry + tmp.hi
 
bic     r2, r5, field_not_M             @ r[1] = d & M
str     r2, [r0, #1*4]
mov     r5, r5, lsr #26                 @ d >>= 26 (ignore hi)
orr     r5, r5, r6, asl #6
 
add     r5, r5, r9                      @ d += t2
str     r5, [r0, #2*4]                  @ r[2] = d
 
add     sp, sp, #48
ldmfd   sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc}
.size   secp256k1_fe_sqr_inner, .-secp256k1_fe_sqr_inner

libsecp256k1/src/tests.c  view on Meta::CPAN

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    }
}
 
static void run_ecdsa_end_to_end(void) {
    int i;
    for (i = 0; i < 64*COUNT; i++) {
        test_ecdsa_end_to_end();
    }
}
 
static int test_ecdsa_der_parse(const unsigned char *sig, size_t siglen, int certainly_der, int certainly_not_der) {
    static const unsigned char zeroes[32] = {0};
 
    int ret = 0;
 
    secp256k1_ecdsa_signature sig_der;
    unsigned char roundtrip_der[2048];
    unsigned char compact_der[64];
    size_t len_der = 2048;
    int parsed_der = 0, valid_der = 0, roundtrips_der = 0;

libsecp256k1/src/tests.c  view on Meta::CPAN

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    valid_der_lax = (secp256k1_memcmp_var(compact_der_lax, zeroes, 32) != 0) && (secp256k1_memcmp_var(compact_der_lax + 32, zeroes, 32) != 0);
}
if (valid_der_lax) {
    ret |= (!secp256k1_ecdsa_signature_serialize_der(CTX, roundtrip_der_lax, &len_der_lax, &sig_der_lax)) << 11;
    roundtrips_der_lax = (len_der_lax == siglen) && secp256k1_memcmp_var(roundtrip_der_lax, sig, siglen) == 0;
}
 
if (certainly_der) {
    ret |= (!parsed_der) << 2;
}
if (certainly_not_der) {
    ret |= (parsed_der) << 17;
}
if (valid_der) {
    ret |= (!roundtrips_der) << 3;
}
 
if (valid_der) {
    ret |= (!roundtrips_der_lax) << 12;
    ret |= (len_der != len_der_lax) << 13;
    ret |= ((len_der != len_der_lax) || (secp256k1_memcmp_var(roundtrip_der_lax, roundtrip_der, len_der) != 0)) << 14;

libsecp256k1/src/tests.c  view on Meta::CPAN

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        /* Modify a byte. */
        sig[testrand_int(*len)] += 1 + testrand_int(255);
        return;
    } else { /* action < 8 */
        /* Modify a bit. */
        sig[testrand_int(*len)] ^= 1 << testrand_bits(3);
        return;
    }
}
 
static void random_ber_signature(unsigned char *sig, size_t *len, int* certainly_der, int* certainly_not_der) {
    int der;
    int nlow[2], nlen[2], nlenlen[2], nhbit[2], nhbyte[2], nzlen[2];
    size_t tlen, elen, glen;
    int indet;
    int n;
 
    *len = 0;
    der = testrand_bits(2) == 0;
    *certainly_der = der;
    *certainly_not_der = 0;
    indet = der ? 0 : testrand_int(10) == 0;
 
    for (n = 0; n < 2; n++) {
        /* We generate two classes of numbers: nlow==1 "low" ones (up to 32 bytes), nlow==0 "high" ones (32 bytes with 129 top bits set, or larger than 32 bytes) */
        nlow[n] = der ? 1 : (testrand_bits(3) != 0);
        /* The length of the number in bytes (the first byte of which will always be nonzero) */
        nlen[n] = nlow[n] ? testrand_int(33) : 32 + testrand_int(200) * testrand_bits(3) / 8;
        CHECK(nlen[n] <= 232);
        /* The top bit of the number. */
        nhbit[n] = (nlow[n] == 0 && nlen[n] == 32) ? 1 : (nlen[n] == 0 ? 0 : testrand_bits(1));
        /* The top byte of the number (after the potential hardcoded 16 0xFF characters for "high" 32 bytes numbers) */
        nhbyte[n] = nlen[n] == 0 ? 0 : (nhbit[n] ? 128 + testrand_bits(7) : 1 + testrand_int(127));
        /* The number of zero bytes in front of the number (which is 0 or 1 in case of DER, otherwise we extend up to 300 bytes) */
        nzlen[n] = der ? ((nlen[n] == 0 || nhbit[n]) ? 1 : 0) : (nlow[n] ? testrand_int(3) : testrand_int(300 - nlen[n]) * testrand_bits(3) / 8);
        if (nzlen[n] > ((nlen[n] == 0 || nhbit[n]) ? 1 : 0)) {
            *certainly_not_der = 1;
        }
        CHECK(nlen[n] + nzlen[n] <= 300);
        /* The length of the length descriptor for the number. 0 means short encoding, anything else is long encoding. */
        nlenlen[n] = nlen[n] + nzlen[n] < 128 ? 0 : (nlen[n] + nzlen[n] < 256 ? 1 : 2);
        if (!der) {
            /* nlenlen[n] max 127 bytes */
            int add = testrand_int(127 - nlenlen[n]) * testrand_bits(4) * testrand_bits(4) / 256;
            nlenlen[n] += add;
            if (add != 0) {
                *certainly_not_der = 1;
            }
        }
        CHECK(nlen[n] + nzlen[n] + nlenlen[n] <= 427);
    }
 
    /* The total length of the data to go, so far */
    tlen = 2 + nlenlen[0] + nlen[0] + nzlen[0] + 2 + nlenlen[1] + nlen[1] + nzlen[1];
    CHECK(tlen <= 856);
 
    /* The length of the garbage inside the tuple. */
    elen = (der || indet) ? 0 : testrand_int(980 - tlen) * testrand_bits(3) / 8;
    if (elen != 0) {
        *certainly_not_der = 1;
    }
    tlen += elen;
    CHECK(tlen <= 980);
 
    /* The length of the garbage after the end of the tuple. */
    glen = der ? 0 : testrand_int(990 - tlen) * testrand_bits(3) / 8;
    if (glen != 0) {
        *certainly_not_der = 1;
    }
    CHECK(tlen + glen <= 990);
 
    /* Write the tuple header. */
    sig[(*len)++] = 0x30;
    if (indet) {
        /* Indeterminate length */
        sig[(*len)++] = 0x80;
        *certainly_not_der = 1;
    } else {
        int tlenlen = tlen < 128 ? 0 : (tlen < 256 ? 1 : 2);
        if (!der) {
            int add = testrand_int(127 - tlenlen) * testrand_bits(4) * testrand_bits(4) / 256;
            tlenlen += add;
            if (add != 0) {
                *certainly_not_der = 1;
            }
        }
        if (tlenlen == 0) {
            /* Short length notation */
            sig[(*len)++] = tlen;
        } else {
            /* Long length notation */
            sig[(*len)++] = 128 + tlenlen;
            assign_big_endian(sig + *len, tlenlen, tlen);
            *len += tlenlen;

libsecp256k1/src/tests.c  view on Meta::CPAN

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    CHECK(tlen <= 1121);
    CHECK(tlen == *len);
}
 
static void run_ecdsa_der_parse(void) {
    int i,j;
    for (i = 0; i < 200 * COUNT; i++) {
        unsigned char buffer[2048];
        size_t buflen = 0;
        int certainly_der = 0;
        int certainly_not_der = 0;
        random_ber_signature(buffer, &buflen, &certainly_der, &certainly_not_der);
        CHECK(buflen <= 2048);
        for (j = 0; j < 16; j++) {
            int ret = 0;
            if (j > 0) {
                damage_array(buffer, &buflen);
                /* We don't know anything anymore about the DERness of the result */
                certainly_der = 0;
                certainly_not_der = 0;
            }
            ret = test_ecdsa_der_parse(buffer, buflen, certainly_der, certainly_not_der);
            if (ret != 0) {
                size_t k;
                fprintf(stderr, "Failure %x on ", ret);
                for (k = 0; k < buflen; k++) {
                    fprintf(stderr, "%02x ", buffer[k]);
                }
                fprintf(stderr, "\n");
            }
            CHECK(ret == 0);
        }



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