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lib/Device/Chip/AVR_HVSP.pm  view on Meta::CPAN

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{
   my $SCI = $_pins{sci};
   my $SDI = $_pins{sdi};
   my $SII = $_pins{sii};
   my $SDO = $_pins{sdo};
 
   my $sdo = 0;
   my $proto = $self->protocol;
 
   # A "byte" transfer consists of 11 clock transitions; idle low. Each bit is
   # clocked in from SDO on the falling edge of clocks 0 to 7, but clocked out
   # of SDI and SII on clocks 1 to 8.
   # We'll therefore toggle the clock 11 times; on each of the first 8 clocks
   # we raise it, then simultaneously lower it, writing out the next out bits
   # and reading in the input.
   # Serial transfer is MSB first in both directions
   #
   # We cheat massively here and rely on pipeline ordering of the actual
   # ->write calls, by writing all 22 of the underlying bit transitions to the
   # underlying device, then waiting on all 11 reads to come back.