Alien-TinyCC
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src/c67-gen.c view on Meta::CPAN
#define RC_C67_B12 0x04000000
#define RC_C67_B13 0x08000000
#define RC_IRET RC_C67_A4 /* function return: integer register */
#define RC_LRET RC_C67_A5 /* function return: second integer register */
#define RC_FRET RC_C67_A4 /* function return: float register */
/* pretty names for the registers */
enum {
TREG_EAX = 0, // really A2
TREG_ECX, // really A3
TREG_EDX, // really B0
TREG_ST0, // really B1
TREG_C67_A4,
TREG_C67_A5,
TREG_C67_B4,
TREG_C67_B5,
TREG_C67_A6,
TREG_C67_A7,
TREG_C67_B6,
TREG_C67_B7,
TREG_C67_A8,
TREG_C67_A9,
TREG_C67_B8,
TREG_C67_B9,
TREG_C67_A10,
TREG_C67_A11,
TREG_C67_B10,
TREG_C67_B11,
TREG_C67_A12,
TREG_C67_A13,
TREG_C67_B12,
TREG_C67_B13,
};
/* return registers for function */
#define REG_IRET TREG_C67_A4 /* single word int return register */
#define REG_LRET TREG_C67_A5 /* second word return register (for long long) */
#define REG_FRET TREG_C67_A4 /* float return register */
/* defined if function parameters must be evaluated in reverse order */
/* #define INVERT_FUNC_PARAMS */
/* defined if structures are passed as pointers. Otherwise structures
are directly pushed on stack. */
/* #define FUNC_STRUCT_PARAM_AS_PTR */
/* pointer size, in bytes */
#define PTR_SIZE 4
/* long double size and alignment, in bytes */
#define LDOUBLE_SIZE 12
#define LDOUBLE_ALIGN 4
/* maximum alignment (for aligned attribute support) */
#define MAX_ALIGN 8
/******************************************************/
/* ELF defines */
#define EM_TCC_TARGET EM_C60
/* relocation type for 32 bit data relocation */
#define R_DATA_32 R_C60_32
#define R_DATA_PTR R_C60_32
#define R_JMP_SLOT R_C60_JMP_SLOT
#define R_COPY R_C60_COPY
#define ELF_START_ADDR 0x00000400
#define ELF_PAGE_SIZE 0x1000
/******************************************************/
#else /* ! TARGET_DEFS_ONLY */
/******************************************************/
#include "tcc.h"
ST_DATA const int reg_classes[NB_REGS] = {
/* eax */ RC_INT | RC_FLOAT | RC_EAX,
// only allow even regs for floats (allow for doubles)
/* ecx */ RC_INT | RC_ECX,
/* edx */ RC_INT | RC_INT_BSIDE | RC_FLOAT | RC_EDX,
// only allow even regs for floats (allow for doubles)
/* st0 */ RC_INT | RC_INT_BSIDE | RC_ST0,
/* A4 */ RC_C67_A4,
/* A5 */ RC_C67_A5,
/* B4 */ RC_C67_B4,
/* B5 */ RC_C67_B5,
/* A6 */ RC_C67_A6,
/* A7 */ RC_C67_A7,
/* B6 */ RC_C67_B6,
/* B7 */ RC_C67_B7,
/* A8 */ RC_C67_A8,
/* A9 */ RC_C67_A9,
/* B8 */ RC_C67_B8,
/* B9 */ RC_C67_B9,
/* A10 */ RC_C67_A10,
/* A11 */ RC_C67_A11,
/* B10 */ RC_C67_B10,
/* B11 */ RC_C67_B11,
/* A12 */ RC_C67_A10,
/* A13 */ RC_C67_A11,
/* B12 */ RC_C67_B10,
/* B13 */ RC_C67_B11
};
// although tcc thinks it is passing parameters on the stack,
// the C67 really passes up to the first 10 params in special
// regs or regs pairs (for 64 bit params). So keep track of
// the stack offsets so we can translate to the appropriate
// reg (pair)
#define NoCallArgsPassedOnStack 10
int NoOfCurFuncArgs;
int TranslateStackToReg[NoCallArgsPassedOnStack];
int ParamLocOnStack[NoCallArgsPassedOnStack];
int TotalBytesPushedOnStack;
#ifndef FALSE
# define FALSE 0
# define TRUE 1
#endif
#undef BOOL
#define BOOL int
#define ALWAYS_ASSERT(x) \
do {\
if (!(x))\
tcc_error("internal compiler error file at %s:%d", __FILE__, __LINE__);\
} while (0)
/******************************************************/
static unsigned long func_sub_sp_offset;
static int func_ret_sub;
static BOOL C67_invert_test;
static int C67_compare_reg;
#ifdef ASSEMBLY_LISTING_C67
FILE *f = NULL;
#endif
void C67_g(int c)
{
int ind1;
#ifdef ASSEMBLY_LISTING_C67
fprintf(f, " %08X", c);
#endif
ind1 = ind + 4;
if (ind1 > (int) cur_text_section->data_allocated)
section_realloc(cur_text_section, ind1);
cur_text_section->data[ind] = c & 0xff;
cur_text_section->data[ind + 1] = (c >> 8) & 0xff;
cur_text_section->data[ind + 2] = (c >> 16) & 0xff;
cur_text_section->data[ind + 3] = (c >> 24) & 0xff;
ind = ind1;
}
/* output a symbol and patch all calls to it */
void gsym_addr(int t, int a)
{
int n, *ptr;
while (t) {
ptr = (int *) (cur_text_section->data + t);
{
Sym *sym;
// extract 32 bit address from MVKH/MVKL
n = ((*ptr >> 7) & 0xffff);
n |= ((*(ptr + 1) >> 7) & 0xffff) << 16;
// define a label that will be relocated
sym = get_sym_ref(&char_pointer_type, cur_text_section, a, 0);
greloc(cur_text_section, sym, t, R_C60LO16);
greloc(cur_text_section, sym, t + 4, R_C60HI16);
// clear out where the pointer was
*ptr &= ~(0xffff << 7);
*(ptr + 1) &= ~(0xffff << 7);
}
t = n;
}
}
void gsym(int t)
{
gsym_addr(t, ind);
}
// these are regs that tcc doesn't really know about,
// but asign them unique values so the mapping routines
// can distinquish them
#define C67_A0 105
#define C67_SP 106
#define C67_B3 107
#define C67_FP 108
#define C67_B2 109
#define C67_CREG_ZERO -1 /* Special code for no condition reg test */
int ConvertRegToRegClass(int r)
{
// only works for A4-B13
return RC_C67_A4 << (r - TREG_C67_A4);
}
// map TCC reg to C67 reg number
int C67_map_regn(int r)
{
if (r == 0) // normal tcc regs
return 0x2; // A2
else if (r == 1) // normal tcc regs
return 3; // A3
else if (r == 2) // normal tcc regs
return 0; // B0
else if (r == 3) // normal tcc regs
return 1; // B1
else if (r >= TREG_C67_A4 && r <= TREG_C67_B13) // these form a pattern of alt pairs
return (((r & 0xfffffffc) >> 1) | (r & 1)) + 2;
else if (r == C67_A0)
return 0; // set to A0 (offset reg)
else if (r == C67_B2)
return 2; // set to B2 (offset reg)
else if (r == C67_B3)
return 3; // set to B3 (return address reg)
else if (r == C67_SP)
src/c67-gen.c view on Meta::CPAN
ALWAYS_ASSERT(C67_map_regs(c) == C67_map_regs(a));
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2
(C67_map_regn(a) << 13) | //src1
(xpath << 12) | //x cross path if opposite sides
(0x27 << 6) | //opcode
(0x8 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side of dest
(0 << 0)); //parallel
} else if (strstr(s, "SHL.S") == s) {
xpath = C67_map_regs(b) ^ C67_map_regs(c);
ALWAYS_ASSERT(C67_map_regs(c) == C67_map_regs(a));
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2
(C67_map_regn(a) << 13) | //src1
(xpath << 12) | //x cross path if opposite sides
(0x33 << 6) | //opcode
(0x8 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side of dest
(0 << 0)); //parallel
} else if (strstr(s, "||ADDK") == s) {
xpath = 0; // no xpath required just use the side of the src/dst
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(b) << 23) | //dst
(a << 07) | //scst16
(0x14 << 2) | //opcode fixed
(C67_map_regs(b) << 1) | //side of dst
(1 << 0)); //parallel
} else if (strstr(s, "ADDK") == s) {
xpath = 0; // no xpath required just use the side of the src/dst
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(b) << 23) | //dst
(a << 07) | //scst16
(0x14 << 2) | //opcode fixed
(C67_map_regs(b) << 1) | //side of dst
(0 << 0)); //parallel
} else if (strstr(s, "NOP") == s) {
C67_g(((a - 1) << 13) | //no of cycles
(0 << 0)); //parallel
} else
ALWAYS_ASSERT(FALSE);
#ifdef ASSEMBLY_LISTING_C67
fprintf(f, " %s %d %d %d\n", s, a, b, c);
#endif
}
//r=reg to load, fr=from reg, symbol for relocation, constant
void C67_MVKL(int r, int fc)
{
C67_asm("MVKL.", fc, r, 0);
}
void C67_MVKH(int r, int fc)
{
C67_asm("MVKH.", fc, r, 0);
}
void C67_STB_SP_A0(int r)
{
C67_asm("STB.D *+SP[A0]", r, 0, 0); // STB r,*+SP[A0]
}
void C67_STH_SP_A0(int r)
{
C67_asm("STH.D *+SP[A0]", r, 0, 0); // STH r,*+SP[A0]
}
void C67_STW_SP_A0(int r)
{
C67_asm("STW.D *+SP[A0]", r, 0, 0); // STW r,*+SP[A0]
}
void C67_STB_PTR(int r, int r2)
{
C67_asm("STB.D *", r, r2, 0); // STB r, *r2
}
void C67_STH_PTR(int r, int r2)
{
C67_asm("STH.D *", r, r2, 0); // STH r, *r2
}
void C67_STW_PTR(int r, int r2)
{
C67_asm("STW.D *", r, r2, 0); // STW r, *r2
}
void C67_STW_PTR_PRE_INC(int r, int r2, int n)
{
C67_asm("STW.D +*", r, r2, n); // STW r, *+r2
}
void C67_PUSH(int r)
{
C67_asm("STW.D SP POST DEC", r, 0, 0); // STW r,*SP--
}
void C67_LDW_SP_A0(int r)
{
C67_asm("LDW.D *+SP[A0]", r, 0, 0); // LDW *+SP[A0],r
}
void C67_LDDW_SP_A0(int r)
{
C67_asm("LDDW.D *+SP[A0]", r, 0, 0); // LDDW *+SP[A0],r
}
src/c67-gen.c view on Meta::CPAN
int stack_pos = 8;
for (t = 0; t < NoCallArgsPassedOnStack; t++) {
if (fc == stack_pos)
break;
stack_pos += TranslateStackToReg[t];
}
// param has been pushed on stack, get it like a local var
fc = ParamLocOnStack[t] - 8;
}
if (size == 8)
element = 4;
else
element = size;
// divide offset in bytes to create word index
C67_MVKL(C67_A0, (fc / element) + 8 / element); //r=reg to load, constant
C67_MVKH(C67_A0, (fc / element) + 8 / element); //r=reg to load, constant
if (size == 1)
C67_STB_SP_A0(r); // STB r, SP[A0]
else if (size == 2)
C67_STH_SP_A0(r); // STH r, SP[A0]
else if (size == 4 || size == 8)
C67_STW_SP_A0(r); // STW r, SP[A0]
if (size == 8) {
C67_ADDK(1, C67_A0); // ADDK 1,A0
C67_STW_SP_A0(r + 1); // STW r, SP[A0]
}
} else {
if (size == 1)
C67_STB_PTR(r, fr); // STB r, *fr
else if (size == 2)
C67_STH_PTR(r, fr); // STH r, *fr
else if (size == 4 || size == 8)
C67_STW_PTR(r, fr); // STW r, *fr
if (size == 8) {
C67_STW_PTR_PRE_INC(r + 1, fr, 1); // STW r, *+fr[1]
}
}
}
}
/* 'is_jmp' is '1' if it is a jump */
static void gcall_or_jmp(int is_jmp)
{
int r;
Sym *sym;
if ((vtop->r & (VT_VALMASK | VT_LVAL)) == VT_CONST) {
/* constant case */
if (vtop->r & VT_SYM) {
/* relocation case */
// get add into A0, then start the jump B3
greloc(cur_text_section, vtop->sym, ind, R_C60LO16); // rem the inst need to be patched
greloc(cur_text_section, vtop->sym, ind + 4, R_C60HI16);
C67_MVKL(C67_A0, 0); //r=reg to load, constant
C67_MVKH(C67_A0, 0); //r=reg to load, constant
C67_IREG_B_REG(0, C67_CREG_ZERO, C67_A0); // B.S2x A0
if (is_jmp) {
C67_NOP(5); // simple jump, just put NOP
} else {
// Call, must load return address into B3 during delay slots
sym = get_sym_ref(&char_pointer_type, cur_text_section, ind + 12, 0); // symbol for return address
greloc(cur_text_section, sym, ind, R_C60LO16); // rem the inst need to be patched
greloc(cur_text_section, sym, ind + 4, R_C60HI16);
C67_MVKL(C67_B3, 0); //r=reg to load, constant
C67_MVKH(C67_B3, 0); //r=reg to load, constant
C67_NOP(3); // put remaining NOPs
}
} else {
/* put an empty PC32 relocation */
ALWAYS_ASSERT(FALSE);
}
} else {
/* otherwise, indirect call */
r = gv(RC_INT);
C67_IREG_B_REG(0, C67_CREG_ZERO, r); // B.S2x r
if (is_jmp) {
C67_NOP(5); // simple jump, just put NOP
} else {
// Call, must load return address into B3 during delay slots
sym = get_sym_ref(&char_pointer_type, cur_text_section, ind + 12, 0); // symbol for return address
greloc(cur_text_section, sym, ind, R_C60LO16); // rem the inst need to be patched
greloc(cur_text_section, sym, ind + 4, R_C60HI16);
C67_MVKL(C67_B3, 0); //r=reg to load, constant
C67_MVKH(C67_B3, 0); //r=reg to load, constant
C67_NOP(3); // put remaining NOPs
}
}
}
/* Return 1 if this function returns via an sret pointer, 0 otherwise */
ST_FUNC int gfunc_sret(CType *vt, CType *ret, int *ret_align) {
*ret_align = 1; // Never have to re-align return values for x86-64
return 1;
}
/* generate function call with address in (vtop->t, vtop->c) and free function
context. Stack entry is popped */
void gfunc_call(int nb_args)
{
int i, r, size = 0;
int args_sizes[NoCallArgsPassedOnStack];
if (nb_args > NoCallArgsPassedOnStack) {
tcc_error("more than 10 function params not currently supported");
// handle more than 10, put some on the stack
}
for (i = 0; i < nb_args; i++) {
if ((vtop->type.t & VT_BTYPE) == VT_STRUCT) {
ALWAYS_ASSERT(FALSE);
} else if ((vtop->type.t & VT_BTYPE) == VT_STRUCT) {
ALWAYS_ASSERT(FALSE);
} else {
/* simple type (currently always same size) */
/* XXX: implicit cast ? */
if ((vtop->type.t & VT_BTYPE) == VT_LLONG) {
tcc_error("long long not supported");
} else if ((vtop->type.t & VT_BTYPE) == VT_LDOUBLE) {
tcc_error("long double not supported");
} else if ((vtop->type.t & VT_BTYPE) == VT_DOUBLE) {
size = 8;
} else {
size = 4;
}
src/c67-gen.c view on Meta::CPAN
loc = 0;
for (i = 0; i < NoOfCurFuncArgs; i++) {
ParamLocOnStack[i] = loc; // remember where the param is
loc += -8;
C67_PUSH(TREG_C67_A4 + i * 2);
if (TranslateStackToReg[i] == 8) {
C67_STW_PTR_PRE_INC(TREG_C67_A4 + i * 2 + 1, C67_SP, 3); // STW r, *+SP[1] (go back and put the other)
}
}
TotalBytesPushedOnStack = -loc;
func_sub_sp_offset = ind; // remember where we put the stack instruction
C67_ADDK(0, C67_SP); // ADDK.L2 loc,SP (just put zero temporarily)
C67_PUSH(C67_A0);
C67_PUSH(C67_B3);
}
/* generate function epilog */
void gfunc_epilog(void)
{
{
int local = (-loc + 7) & -8; // stack must stay aligned to 8 bytes for LDDW instr
C67_POP(C67_B3);
C67_NOP(4); // NOP wait for load
C67_IREG_B_REG(0, C67_CREG_ZERO, C67_B3); // B.S2 B3
C67_POP(C67_FP);
C67_ADDK(local, C67_SP); // ADDK.L2 loc,SP
C67_Adjust_ADDK((int *) (cur_text_section->data +
func_sub_sp_offset),
-local + TotalBytesPushedOnStack);
C67_NOP(3); // NOP
}
}
/* generate a jump to a label */
int gjmp(int t)
{
int ind1 = ind;
C67_MVKL(C67_A0, t); //r=reg to load, constant
C67_MVKH(C67_A0, t); //r=reg to load, constant
C67_IREG_B_REG(0, C67_CREG_ZERO, C67_A0); // [!R] B.S2x A0
C67_NOP(5);
return ind1;
}
/* generate a jump to a fixed address */
void gjmp_addr(int a)
{
Sym *sym;
// I guess this routine is used for relative short
// local jumps, for now just handle it as the general
// case
// define a label that will be relocated
sym = get_sym_ref(&char_pointer_type, cur_text_section, a, 0);
greloc(cur_text_section, sym, ind, R_C60LO16);
greloc(cur_text_section, sym, ind + 4, R_C60HI16);
gjmp(0); // place a zero there later the symbol will be added to it
}
/* generate a test. set 'inv' to invert test. Stack entry is popped */
int gtst(int inv, int t)
{
int ind1, n;
int v, *p;
v = vtop->r & VT_VALMASK;
if (v == VT_CMP) {
/* fast case : can jump directly since flags are set */
// C67 uses B2 sort of as flags register
ind1 = ind;
C67_MVKL(C67_A0, t); //r=reg to load, constant
C67_MVKH(C67_A0, t); //r=reg to load, constant
if (C67_compare_reg != TREG_EAX && // check if not already in a conditional test reg
C67_compare_reg != TREG_EDX &&
C67_compare_reg != TREG_ST0 && C67_compare_reg != C67_B2) {
C67_MV(C67_compare_reg, C67_B2);
C67_compare_reg = C67_B2;
}
C67_IREG_B_REG(C67_invert_test ^ inv, C67_compare_reg, C67_A0); // [!R] B.S2x A0
C67_NOP(5);
t = ind1; //return where we need to patch
} else if (v == VT_JMP || v == VT_JMPI) {
/* && or || optimization */
if ((v & 1) == inv) {
/* insert vtop->c jump list in t */
p = &vtop->c.i;
// I guess the idea is to traverse to the
// null at the end of the list and store t
// there
n = *p;
while (n != 0) {
p = (int *) (cur_text_section->data + n);
// extract 32 bit address from MVKH/MVKL
n = ((*p >> 7) & 0xffff);
n |= ((*(p + 1) >> 7) & 0xffff) << 16;
}
*p |= (t & 0xffff) << 7;
*(p + 1) |= ((t >> 16) & 0xffff) << 7;
t = vtop->c.i;
} else {
t = gjmp(t);
gsym(vtop->c.i);
}
} else {
( run in 0.442 second using v1.01-cache-2.11-cpan-71847e10f99 )