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#if defined(_MSC_VER) && !defined(__clang__)
/* MSVC. */
#if _MSC_VER >= 1400 && !defined(DRFLAC_NO_SSE2) /* 2005 */
#define DRFLAC_SUPPORT_SSE2
#endif
#if _MSC_VER >= 1600 && !defined(DRFLAC_NO_SSE41) /* 2010 */
#define DRFLAC_SUPPORT_SSE41
#endif
#elif defined(__clang__) || (defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 3)))
/* Assume GNUC-style. */
#if defined(__SSE2__) && !defined(DRFLAC_NO_SSE2)
#define DRFLAC_SUPPORT_SSE2
#endif
#if defined(__SSE4_1__) && !defined(DRFLAC_NO_SSE41)
#define DRFLAC_SUPPORT_SSE41
#endif
#endif
/* If at this point we still haven't determined compiler support for the intrinsics just fall back to __has_include. */
#if !defined(__GNUC__) && !defined(__clang__) && defined(__has_include)
#if !defined(DRFLAC_SUPPORT_SSE2) && !defined(DRFLAC_NO_SSE2) && __has_include(<emmintrin.h>)
#define DRFLAC_SUPPORT_SSE2
#endif
#if !defined(DRFLAC_SUPPORT_SSE41) && !defined(DRFLAC_NO_SSE41) && __has_include(<smmintrin.h>)
#define DRFLAC_SUPPORT_SSE41
#endif
#endif
#if defined(DRFLAC_SUPPORT_SSE41)
#include <smmintrin.h>
#elif defined(DRFLAC_SUPPORT_SSE2)
#include <emmintrin.h>
#endif
#endif
#if defined(DRFLAC_ARM)
#if !defined(DRFLAC_NO_NEON) && (defined(__ARM_NEON) || defined(__aarch64__) || defined(_M_ARM64))
#define DRFLAC_SUPPORT_NEON
#include <arm_neon.h>
#endif
#endif
#endif
/* Compile-time CPU feature support. */
#if !defined(DR_FLAC_NO_SIMD) && (defined(DRFLAC_X86) || defined(DRFLAC_X64))
#if defined(_MSC_VER) && !defined(__clang__)
#if _MSC_VER >= 1400
#include <intrin.h>
static void drflac__cpuid(int info[4], int fid)
{
__cpuid(info, fid);
}
#else
#define DRFLAC_NO_CPUID
#endif
#else
#if defined(__GNUC__) || defined(__clang__)
static void drflac__cpuid(int info[4], int fid)
{
/*
It looks like the -fPIC option uses the ebx register which GCC complains about. We can work around this by just using a different register, the
specific register of which I'm letting the compiler decide on. The "k" prefix is used to specify a 32-bit register. The {...} syntax is for
supporting different assembly dialects.
What's basically happening is that we're saving and restoring the ebx register manually.
*/
#if defined(DRFLAC_X86) && defined(__PIC__)
__asm__ __volatile__ (
"xchg{l} {%%}ebx, %k1;"
"cpuid;"
"xchg{l} {%%}ebx, %k1;"
: "=a"(info[0]), "=&r"(info[1]), "=c"(info[2]), "=d"(info[3]) : "a"(fid), "c"(0)
);
#else
__asm__ __volatile__ (
"cpuid" : "=a"(info[0]), "=b"(info[1]), "=c"(info[2]), "=d"(info[3]) : "a"(fid), "c"(0)
);
#endif
}
#else
#define DRFLAC_NO_CPUID
#endif
#endif
#else
#define DRFLAC_NO_CPUID
#endif
static DRFLAC_INLINE drflac_bool32 drflac_has_sse2(void)
{
#if defined(DRFLAC_SUPPORT_SSE2)
#if (defined(DRFLAC_X64) || defined(DRFLAC_X86)) && !defined(DRFLAC_NO_SSE2)
#if defined(DRFLAC_X64)
return DRFLAC_TRUE; /* 64-bit targets always support SSE2. */
#elif (defined(_M_IX86_FP) && _M_IX86_FP == 2) || defined(__SSE2__)
return DRFLAC_TRUE; /* If the compiler is allowed to freely generate SSE2 code we can assume support. */
#else
#if defined(DRFLAC_NO_CPUID)
return DRFLAC_FALSE;
#else
int info[4];
drflac__cpuid(info, 1);
return (info[3] & (1 << 26)) != 0;
#endif
#endif
#else
return DRFLAC_FALSE; /* SSE2 is only supported on x86 and x64 architectures. */
#endif
#else
return DRFLAC_FALSE; /* No compiler support. */
#endif
}
static DRFLAC_INLINE drflac_bool32 drflac_has_sse41(void)
{
#if defined(DRFLAC_SUPPORT_SSE41)
#if (defined(DRFLAC_X64) || defined(DRFLAC_X86)) && !defined(DRFLAC_NO_SSE41)
#if defined(DRFLAC_X64)
return DRFLAC_TRUE; /* 64-bit targets always support SSE4.1. */
#elif (defined(_M_IX86_FP) && _M_IX86_FP == 2) || defined(__SSE4_1__)
return DRFLAC_TRUE; /* If the compiler is allowed to freely generate SSE41 code we can assume support. */
#else
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