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libjit/jit/jit-rules-x86-64.ins  view on Meta::CPAN

JIT_OP_DNEG:
	[xreg] -> {
		/* Simply toggle the sign */
		jit_ulong values[2] = {0x8000000000000000, 0x8000000000000000};

		_jit_plopd_reg_imm(gen, &inst, XMM_XORP, $1, &(values[0]));
	}

/*
 * native float versions
 */
JIT_OP_NFABS: stack
	[freg] -> {
		x86_64_fabs(inst);
	}

JIT_OP_NFNEG:  stack
	[freg] -> {
		x86_64_fchs(inst);
	}

/*
 * Bitwise opcodes.
 */

JIT_OP_IAND: commutative
	[reg, imm] -> {
		x86_64_and_reg_imm_size(inst, $1, $2, 4);
	}
	[reg, local] -> {
		x86_64_and_reg_membase_size(inst, $1, X86_64_RBP, $2, 4);
	}
	[reg, reg] -> {
		x86_64_and_reg_reg_size(inst, $1, $2, 4);
	}

JIT_OP_IOR: commutative
	[reg, imm] -> {
		x86_64_or_reg_imm_size(inst, $1, $2, 4);
	}
	[reg, local] -> {
		x86_64_or_reg_membase_size(inst, $1, X86_64_RBP, $2, 4);
	}
	[reg, reg] -> {
		x86_64_or_reg_reg_size(inst, $1, $2, 4);
	}

JIT_OP_IXOR: commutative
	[reg, imm] -> {
		x86_64_xor_reg_imm_size(inst, $1, $2, 4);
	}
	[reg, local] -> {
		x86_64_xor_reg_membase_size(inst, $1, X86_64_RBP, $2, 4);
	}
	[reg, reg] -> {
		x86_64_xor_reg_reg_size(inst, $1, $2, 4);
	}

JIT_OP_INOT:
	[reg] -> {
		x86_64_not_reg_size(inst, $1, 4);
	}

JIT_OP_ISHL:
	[reg, imm] -> {
		x86_64_shl_reg_imm_size(inst, $1, ($2 & 0x1F), 4);
	}
	[sreg, reg("rcx")] -> {
		x86_64_shl_reg_size(inst, $1, 4);
	}

JIT_OP_ISHR:
	[reg, imm] -> {
		x86_64_sar_reg_imm_size(inst, $1, ($2 & 0x1F), 4);
	}
	[sreg, reg("rcx")] -> {
		x86_64_sar_reg_size(inst, $1, 4);
	}

JIT_OP_ISHR_UN:
	[reg, imm] -> {
		x86_64_shr_reg_imm_size(inst, $1, ($2 & 0x1F), 4);
	}
	[sreg, reg("rcx")] -> {
		x86_64_shr_reg_size(inst, $1, 4);
	}

JIT_OP_LAND: commutative
	[reg, imms32] -> {
		x86_64_and_reg_imm_size(inst, $1, $2, 8);
	}
	[reg, local] -> {
		x86_64_and_reg_membase_size(inst, $1, X86_64_RBP, $2, 8);
	}
	[reg, reg] -> {
		x86_64_and_reg_reg_size(inst, $1, $2, 8);
	}

JIT_OP_LOR: commutative
	[reg, imms32] -> {
		x86_64_or_reg_imm_size(inst, $1, $2, 8);
	}
	[reg, local] -> {
		x86_64_or_reg_membase_size(inst, $1, X86_64_RBP, $2, 8);
	}
	[reg, reg] -> {
		x86_64_or_reg_reg_size(inst, $1, $2, 8);
	}

JIT_OP_LXOR: commutative
	[reg, imms32] -> {
		x86_64_xor_reg_imm_size(inst, $1, $2, 8);
	}
	[reg, local] -> {
		x86_64_xor_reg_membase_size(inst, $1, X86_64_RBP, $2, 8);
	}
	[reg, reg] -> {
		x86_64_xor_reg_reg_size(inst, $1, $2, 8);
	}

JIT_OP_LNOT:
	[reg] -> {
		x86_64_not_reg_size(inst, $1, 8);
	}

JIT_OP_LSHL:
	[reg, imm] -> {
		x86_64_shl_reg_imm_size(inst, $1, ($2 & 0x3F), 8);
	}
	[sreg, reg("rcx")] -> {
		x86_64_shl_reg_size(inst, $1, 8);
	}

JIT_OP_LSHR:
	[reg, imm] -> {
		x86_64_sar_reg_imm_size(inst, $1, ($2 & 0x3F), 8);
	}
	[sreg, reg("rcx")] -> {
		x86_64_sar_reg_size(inst, $1, 8);
	}

JIT_OP_LSHR_UN:
	[reg, imm] -> {
		x86_64_shr_reg_imm_size(inst, $1, ($2 & 0x3F), 8);
	}
	[sreg, reg("rcx")] -> {
		x86_64_shr_reg_size(inst, $1, 8);
	}

/*
 * Branch opcodes.
 */

JIT_OP_BR: branch
	[] -> {
		inst = output_branch(func, inst, 0xEB /* jmp */, insn);
	}

JIT_OP_BR_IFALSE: branch
	[reg] -> {
		x86_64_test_reg_reg_size(inst, $1, $1, 4);
		inst = output_branch(func, inst, 0x74 /* eq */, insn);
	}

JIT_OP_BR_ITRUE: branch
	[reg] -> {
		x86_64_test_reg_reg_size(inst, $1, $1, 4);
		inst = output_branch(func, inst, 0x75 /* ne */, insn);
	}

JIT_OP_BR_IEQ: branch, commutative
	[reg, immzero] -> {
		x86_64_test_reg_reg_size(inst, $1, $1, 4);
		inst = output_branch(func, inst, 0x74 /* eq */, insn);
	}
	[reg, imm] -> {
		x86_64_cmp_reg_imm_size(inst, $1, $2, 4);
		inst = output_branch(func, inst, 0x74 /* eq */, insn);
	}
	[reg, local] -> {
		x86_64_cmp_reg_membase_size(inst, $1, X86_64_RBP, $2, 4);
		inst = output_branch(func, inst, 0x74 /* eq */, insn);
	}