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libjit/jit/jit-gen-x86-64.h  view on Meta::CPAN

 * mul: multiply RDX:RAX = RAX * operand
 * is_signed == 0 -> unsigned multiplication
 * signed multiplication otherwise.
 */
#define x86_64_mul_reg_issigned_size(inst, reg, is_signed, size) \
	do { \
		x86_64_alu1_reg_size((inst), 0xf6, ((is_signed) ? 5 : 4), (reg), (size)); \
	} while(0)

#define x86_64_mul_regp_issigned_size(inst, regp, is_signed, size) \
	do { \
		x86_64_alu1_regp_size((inst), 0xf6, ((is_signed) ? 5 : 4), (regp), (size)); \
	} while(0)

#define x86_64_mul_mem_issigned_size(inst, mem, is_signed, size) \
	do { \
		x86_64_alu1_mem_size((inst), 0xf6, ((is_signed) ? 5 : 4), (mem), (size)); \
	} while(0)

#define x86_64_mul_membase_issigned_size(inst, basereg, disp, is_signed, size) \
	do { \
		x86_64_alu1_membase_size((inst), 0xf6, ((is_signed) ? 5 : 4), (basereg), (disp), (size)); \
	} while(0)

#define x86_64_mul_memindex_issigned_size(inst, basereg, disp, indexreg, shift, is_signed, size) \
	do { \
		x86_64_alu1_memindex_size((inst), 0xf6, ((is_signed) ? 5 : 4), (basereg), (disp), (indexreg), (shift), (size)); \
	} while(0)

/*
 * neg 
 */
#define x86_64_neg_reg_size(inst, reg, size) \
	do { \
		x86_64_alu1_reg_size((inst), 0xf6, 3, (reg), (size)); \
	} while(0)

#define x86_64_neg_regp_size(inst, regp, size) \
	do { \
		x86_64_alu1_regp_size((inst), 0xf6, 3, (regp), (size)); \
	} while(0)

#define x86_64_neg_mem_size(inst, mem, size) \
	do { \
		x86_64_alu1_mem_size((inst), 0xf6, 3, (mem), (size)); \
	} while(0)

#define x86_64_neg_membase_size(inst, basereg, disp, size) \
	do { \
		x86_64_alu1_membase_size((inst), 0xf6, 3, (basereg), (disp), (size)); \
	} while(0)

#define x86_64_neg_memindex_size(inst, basereg, disp, indexreg, shift, size) \
	do { \
		x86_64_alu1_memindex_size((inst), 0xf6, 3, (basereg), (disp), (indexreg), (shift), (size)); \
	} while(0)

/*
 * not
 */
#define x86_64_not_reg_size(inst, reg, size) \
	do { \
		x86_64_alu1_reg_size((inst), 0xf6, 2, (reg), (size)); \
	} while(0)

#define x86_64_not_regp_size(inst, regp, size) \
	do { \
		x86_64_alu1_regp_size((inst), 0xf6, 2, (regp), (size)); \
	} while(0)

#define x86_64_not_mem_size(inst, mem, size) \
	do { \
		x86_64_alu1_mem_size((inst), 0xf6, 2, (mem), (size)); \
	} while(0)

#define x86_64_not_membase_size(inst, basereg, disp, size) \
	do { \
		x86_64_alu1_membase_size((inst), 0xf6, 2, (basereg), (disp), (size)); \
	} while(0)

#define x86_64_not_memindex_size(inst, basereg, disp, indexreg, shift, size) \
	do { \
		x86_64_alu1_memindex_size((inst), 0xf6, 2, (basereg), (disp), (indexreg), (shift), (size)); \
	} while(0)

/*
 * Note: x86_64_clear_reg () changes the condition code!
 */
#define x86_64_clear_reg(inst, reg) \
	x86_64_xor_reg_reg_size((inst), (reg), (reg), 4)

/*
 * shift instructions
 */
#define x86_64_shift_reg_imm_size(inst, opc, dreg, imm, size) \
	do { \
		if((imm) == 1) \
		{ \
			if((size) == 2) \
			{ \
				*(inst)++ = (unsigned char)0x66; \
			} \
			x86_64_rex_emit((inst), (size), 0, 0, (dreg)); \
			x86_64_opcode1_emit((inst), 0xd0, (size)); \
			x86_64_reg_emit((inst), (opc), (dreg)); \
		} \
		else \
		{ \
			if((size) == 2) \
			{ \
				*(inst)++ = (unsigned char)0x66; \
			} \
			x86_64_rex_emit((inst), (size), 0, 0, (dreg)); \
			x86_64_opcode1_emit((inst), 0xc0, (size)); \
			x86_64_reg_emit((inst), (opc), (dreg)); \
			x86_imm_emit8((inst), (imm)); \
		} \
	} while(0)

#define x86_64_shift_mem_imm_size(inst, opc, mem, imm, size) \
	do { \
		if((imm) == 1) \
		{ \
			if((size) == 2) \
			{ \
				*(inst)++ = (unsigned char)0x66; \
			} \
			x86_64_rex_emit((inst), (size), 0, 0, 0); \
			x86_64_opcode1_emit((inst), 0xd0, (size)); \
			x86_64_mem_emit((inst), (opc), (mem)); \
		} \
		else \
		{ \
			if((size) == 2) \
			{ \
				*(inst)++ = (unsigned char)0x66; \
			} \
			x86_64_rex_emit((inst), (size), 0, 0, 0); \
			x86_64_opcode1_emit((inst), 0xc0, (size)); \
			x86_64_mem_emit((inst), (opc), (mem)); \
			x86_imm_emit8((inst), (imm)); \