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libjit/jit/jit-gen-arm.h  view on Meta::CPAN

	switch ((size)) {	\
		case 1: arm_store_membase_byte((inst), (reg), (basereg), (disp)); break;	\
		case 2: arm_store_membase_short((inst), (reg), (basereg), (disp)); break;	\
		case 4: arm_store_membase((inst), (reg), (basereg), (disp)); break;	\
		default: jit_assert(0);	\
	}	\
} while(0);

/**
* Set the value of "reg" to the "size"-bytes-long value held in memory at position basereg+disp
* NB: can destroys the content of ARM_WORK because of arm_store_membase_short
*/
#define arm_mov_reg_membase(inst,reg,basereg,disp,size)	\
do {	\
	switch ((size)) {	\
		case 1: arm_load_membase_byte((inst), (reg), (basereg), (disp)); break;	\
		case 2: arm_load_membase_short((inst), (reg), (basereg), (disp)); break;	\
		case 4: arm_load_membase((inst), (reg), (basereg), (disp)); break;	\
		default: jit_assert(0);	\
}	\
} while(0);

/*
 * Clear a register to zero.
 */
#define	arm_clear_reg(inst,reg)	\
			do { \
				arm_mov_reg_imm8((inst), (reg), 0); \
			} while (0)

/*
 * No-operation instruction.
 */
#define	arm_nop(inst)	arm_mov_reg_reg((inst), ARM_R0, ARM_R0)

/*
 * Perform a shift operation.
 */
#define	arm_shift_reg_reg(inst,opc,dreg,sreg1,sreg2) \
			do { \
				arm_inst_add((inst), arm_execute | \
							(((unsigned int)ARM_MOV) << 21) | \
							(((unsigned int)(dreg)) << 12) | \
							(((unsigned int)(sreg2)) << 8) | \
							(((unsigned int)(opc)) << 5) | \
							 ((unsigned int)(1 << 4)) | \
							 ((unsigned int)(sreg1))); \
			} while (0)
#define	arm_shift_reg_imm8(inst,opc,dreg,sreg,imm) \
			do { \
				arm_inst_add((inst), arm_execute | \
							(((unsigned int)ARM_MOV) << 21) | \
							(((unsigned int)(dreg)) << 12) | \
							(((unsigned int)(opc)) << 5) | \
							(((unsigned int)(imm)) << 7) | \
							 ((unsigned int)(sreg))); \
			} while (0)

/*
 * Perform a multiplication instruction.  Note: ARM instruction rules
 * say that dreg should not be the same as sreg2, so we swap the order
 * of the arguments if that situation occurs.  We assume that sreg1
 * and sreg2 are distinct registers.
 */
#define arm_mul_reg_reg(inst,dreg,sreg1,sreg2)	\
			do { \
				if((dreg) != (sreg2)) \
				{ \
					arm_inst_add((inst), arm_prefix(0x00000090) | \
								(((unsigned int)(dreg)) << 16) | \
								(((unsigned int)(sreg1)) << 8) | \
								 ((unsigned int)(sreg2))); \
				} \
				else \
				{ \
					arm_inst_add((inst), arm_prefix(0x00000090) | \
								(((unsigned int)(dreg)) << 16) | \
								(((unsigned int)(sreg2)) << 8) | \
								 ((unsigned int)(sreg1))); \
				} \
			} while (0)

#ifdef JIT_ARM_HAS_FPA
/*
 * Perform a binary operation on floating-point arguments.
 */
#define	arm_alu_freg_freg(inst,opc,dreg,sreg1,sreg2)	\
			do { \
				arm_inst_add((inst), arm_prefix(0x0E000180) | \
							(((unsigned int)(opc)) << 20) | \
							(((unsigned int)(dreg)) << 12) | \
							(((unsigned int)(sreg1)) << 16) | \
							 ((unsigned int)(sreg2))); \
			} while (0)
#define	arm_alu_freg_freg_32(inst,opc,dreg,sreg1,sreg2)	\
			do { \
				arm_inst_add((inst), arm_prefix(0x0E000100) | \
							(((unsigned int)(opc)) << 20) | \
							(((unsigned int)(dreg)) << 12) | \
							(((unsigned int)(sreg1)) << 16) | \
							 ((unsigned int)(sreg2))); \
			} while (0)

/*
 * Perform a unary operation on floating-point arguments.
 */
#define	arm_alu_freg(inst,opc,dreg,sreg)	\
			do { \
				arm_inst_add((inst), arm_prefix(0x0E008180) | \
							(((unsigned int)(opc)) << 20) | \
							(((unsigned int)(dreg)) << 12) | \
							 ((unsigned int)(sreg))); \
			} while (0)
#define	arm_alu_freg_32(inst,opc,dreg,sreg)	\
			do { \
				arm_inst_add((inst), arm_prefix(0x0E008100) | \
							(((unsigned int)(opc)) << 20) | \
							(((unsigned int)(dreg)) << 12) | \
							 ((unsigned int)(sreg))); \
			} while (0)