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        MAX7219_REG_DIGIT_0     => 0x01,
        MAX7219_REG_DIGIT_1     => 0x02,
        MAX7219_REG_DIGIT_2     => 0x03,
        MAX7219_REG_DIGIT_3     => 0x04,
        MAX7219_REG_DIGIT_4     => 0x05,
        MAX7219_REG_DIGIT_5     => 0x06,
        MAX7219_REG_DIGIT_6     => 0x07,
        MAX7219_REG_DIGIT_7     => 0x08,
        MAX7219_REG_DECODE_MODE => 0x09,
        MAX7219_REG_INTENSITY   => 0x0A,
        MAX7219_REG_SCAN_LIMIT  => 0x0B,
        MAX7219_REG_SHUTDOWN    => 0x0C,
        MAX7219_REG_TEST        => 0x0F,
    },
    
    hilink => {
        HILINK_CONNSTATUS_CONNECTING     => 900,
        HILINK_CONNSTATUS_CONNECTED      => 901,
        HILINK_CONNSTATUS_DISCONNECTED   => 902,
        HILINK_CONNSTATUS_DISCONNECTING  => 903,
    },
    
    mfrc522 => {
        ## MIFARE STATUS CODES
        MFRC522_STATUS_OK                => 1,	#// Success
		MFRC522_STATUS_ERROR             => 2,	#// Error in communication
		MFRC522_STATUS_COLLISION         => 3,	#// Collission detected
		MFRC522_STATUS_TIMEOUT           => 4,	#// Timeout in communication.
		MFRC522_STATUS_NO_ROOM           => 5,	#// A buffer is not big enough.
		MFRC522_STATUS_INTERNAL_ERROR    => 6,	#// Internal error in the code. Should not happen ;-)
		MFRC522_STATUS_INVALID           => 7,	#// Invalid argument.
		MFRC522_STATUS_CRC_WRONG         => 8,	#// The CRC_A does not match
        
        MFRC522_STATUS_UNSUPPORTED_TYPE  => 9,
        MFRC522_STATUS_BLOCK_NOT_ALLOWED => 10,
        MFRC522_STATUS_BAD_PARAM         => 11,
        
		MFRC522_STATUS_MIFARE_NACK       => 0xff, #// A MIFARE PICC responded with NAK.
        
        ## MF522 MFRC522 error codes.
        MFRC522_ERROR_OK         => 0,         # Everything A-OK.
        MFRC522_ERROR_NOTAGERR   => 1,         # No tag error
        MFRC522_ERROR_ERR        => 2,         # General error

        # MF522 Command word
        MFRC522_IDLE          => 0x00,      # NO action; Cancel the current command
        MFRC522_MEM           => 0x01,      # Store 25 byte into the internal buffer.
        MFRC522_GENID         => 0x02,      # Generates a 10 byte random ID number.
        MFRC522_CALCCRC       => 0x03,      # CRC Calculate or selftest.
        MFRC522_TRANSMIT      => 0x04,      # Transmit data
        MFRC522_NOCMDCH       => 0x07,      # No command change.
        MFRC522_RECEIVE       => 0x08,      # Receive Data
        MFRC522_TRANSCEIVE    => 0x0C,      # Transmit and receive data,
        MFRC522_AUTHENT       => 0x0E,      # Authentication Key
        MFRC522_SOFTRESET     => 0x0F,      # Reset

        # Mifare_One tag command word
        MIFARE_REQIDL            => 0x26,      # find the antenna area does not enter hibernation
        MIFARE_REQALL            => 0x52,      # find all the tags antenna area
        MIFARE_ANTICOLL          => 0x88,      # anti-collision
        MIFARE_CASCADE           => 0x88,      # cascade tag
        MIFARE_SELECTTAG         => 0x93,      # selection tag
        MIFARE_SELECT_CL1        => 0x93,
        MIFARE_SELECT_CL2        => 0x95,
        MIFARE_SELECT_CL3        => 0x97,
        MIFARE_AUTHENT1A         => 0x60,      # authentication key A
        MIFARE_AUTHENT1B         => 0x61,      # authentication key B
        MIFARE_READ              => 0x30,      # Read Block
        MIFARE_WRITE             => 0xA0,      # write block
        MIFARE_DECREMENT         => 0xC0,      # debit
        MIFARE_INCREMENT         => 0xC1,      # recharge
        MIFARE_RESTORE           => 0xC2,      # transfer block data to the buffer
        MIFARE_TRANSFER          => 0xB0,      # save the data in the buffer
        MIFARE_HALT              => 0x50,      # Sleep


        #------------------ MFRC522 registers---------------
        #Page 0:Command and Status
        MFRC522_REG_Reserved00            => 0x00,
        MFRC522_REG_CommandReg            => 0x01,
        MFRC522_REG_CommIEnReg            => 0x02,
        MFRC522_REG_DivIEnReg             => 0x03,
        MFRC522_REG_CommIrqReg            => 0x04,
        MFRC522_REG_DivIrqReg             => 0x05,
        MFRC522_REG_ErrorReg              => 0x06,
        MFRC522_REG_Status1Reg            => 0x07,
        MFRC522_REG_Status2Reg            => 0x08,
        MFRC522_REG_FIFODataReg           => 0x09,
        MFRC522_REG_FIFOLevelReg          => 0x0A,
        MFRC522_REG_WaterLevelReg         => 0x0B,
        MFRC522_REG_ControlReg            => 0x0C,
        MFRC522_REG_BitFramingReg         => 0x0D,
        MFRC522_REG_CollReg               => 0x0E,
        MFRC522_REG_Reserved01            => 0x0F,
        #Page 1:Command
        MFRC522_REG_Reserved10            => 0x10,
        MFRC522_REG_ModeReg               => 0x11,
        MFRC522_REG_TxModeReg             => 0x12,
        MFRC522_REG_RxModeReg             => 0x13,
        MFRC522_REG_TxControlReg          => 0x14,
        MFRC522_REG_TxAutoReg             => 0x15,
        MFRC522_REG_TxSelReg              => 0x16,
        MFRC522_REG_RxSelReg              => 0x17,
        MFRC522_REG_RxThresholdReg        => 0x18,
        MFRC522_REG_DemodReg              => 0x19,
        MFRC522_REG_Reserved11            => 0x1A,
        MFRC522_REG_Reserved12            => 0x1B,
        MFRC522_REG_MifareReg             => 0x1C,
        MFRC522_REG_Reserved13            => 0x1D,
        MFRC522_REG_Reserved14            => 0x1E,
        MFRC522_REG_SerialSpeedReg        => 0x1F,
        #Page 2:CFG
        MFRC522_REG_Reserved20            => 0x20,
        MFRC522_REG_CRCResultRegM         => 0x21,
        MFRC522_REG_CRCResultRegH         => 0x21,
        MFRC522_REG_CRCResultRegL         => 0x22,
        MFRC522_REG_Reserved21            => 0x23,
        MFRC522_REG_ModWidthReg           => 0x24,
        MFRC522_REG_Reserved22            => 0x25,
        MFRC522_REG_RFCfgReg              => 0x26,
        MFRC522_REG_GsNReg                => 0x27,