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lib/Device/Chip/CC1101.pm  view on Meta::CPAN

      my ( $rssi, $lqi ) = unpack( "c C", substr( $bytes, -2, 2, "" ) );

      # RSSI is 2s complement in 0.5dBm units offset from -74dBm
      $ret{RSSI} = $rssi / 2 - 74;

      # LQI/CRC_OK
      $ret{LQI}    = $lqi & 0x7F;
      $ret{CRC_OK} = !!( $lqi & 0x80 );
   }

   $ret{data} = $bytes;

   return \%ret;
}

=head2 transmit

   await $chip->transmit( $bytes );

Enters TX mode and sends a packet containing the given bytes.

This method automatically handles prepending the packet length if the chip is
configured in variable-length packet mode.

=cut

async method transmit ( $bytes )
{
   my $fixedlen = $_cached_config{LENGTH_CONFIG} eq "fixed";

   my $pktlen = length $bytes;
   if( $fixedlen ) {
      $pktlen == $_cached_config{PACKET_LENGTH} or
         croak "Expected a packet $_cached_config{PACKET_LENGTH} bytes long";
   }
   else {
      # Ensure we can't overflow either TX or RX FIFO
      $pktlen <= 62 or
         croak "Expected no more than 62 bytes of packet data"
   }

   await $self->start_tx;

   $bytes = pack "C a*", $pktlen, $bytes if !$fixedlen;

   await $self->write_txfifo( $bytes );

   # Transmit should definitely be over in well under 50msec
   my $deadline = gettimeofday + 0.050;

   while( await( $self->read_chipstatus_tx )->{STATE} eq "TX" ) {
      gettimeofday < $deadline or croak "Timed out waiting for TX to complete";
      await Future::IO->sleep( $_poll_interval );
   }
}

{
   while( readline DATA ) {
      chomp;
      next if m/^#/;
      my ( $name, $fields ) = split m/\|/, $_;

      $PRESET_MODES{$name} = +{
         map { m/(.*?)=(.*)/ } split m/,/, $fields
      };
   }

   %BANDS = (
      "433MHz" => {
         FREQ    => 1091426,
         # From the datasheet presuming 433MHz on multilayer inductors
         PATABLE => "12.0E.1D.34.60.84.C8.C0",
      },

      "868MHz" => {
         FREQ    => 2188650,
         # From the datasheet presuming 868MHz on multilayer inductors
         PATABLE => "03.0F.1E.27.50.81.CB.C2",
      },
   );
}

0x55AA;

=head1 TODO

=over 4

=item *

Polling/interrupts to wait for RX packet

=item *

Support addressing modes in L</transmit> and L</receive>

=back

=head1 AUTHOR

Paul Evans <leonerd@leonerd.org.uk>

=cut

__DATA__
# The following data is automatically generated by update-configs.pl
common|FOC_BS_CS_GATE=,FREQ=2188650,FS_AUTOCAL=on-unidle,PO_TIMEOUT=x64
ASK-4.8kb|CHANBW_E=3,DEVIATION_M=0,DRATE_E=7,DRATE_M=131,FREQ_IF=6,FSCAL=3928621087,MAX_DVGA_GAIN=not-top,MOD_FORMAT=ASK,SYNC_MODE=15/16
GFSK-1.2kb|CCA_MODE=always,CHANBW_E=3,CHANBW_M=3,CHANSPC_E=0,DEVIATION_E=1,DEVIATION_M=5,DRATE_E=5,DRATE_M=131,FEC_EN=1,FREQ_IF=8,FSCAL=2836004881,MOD_FORMAT=GFSK,PA_POWER=7,RXOFF_MODE=RX,SYNC_MODE=30/32
GFSK-100kb|AGC_LNA_PRIORITY=lna-first,BS_PRE_KI=KI,BS_PRE_KP=2KP,CCA_MODE=always,CHANBW_E=1,CHANBW_M=1,CHANSPC_E=0,DRATE_E=11,DRATE_M=248,FEC_EN=1,FILTER_LENGTH=32sa,FOC_LIMIT=BW/8,FOC_PRE_K=4K,FREQ_IF=8,FSCAL=3926523921,LNA2MIX_CURRENT=3,LNA_CURRENT...
GFSK-38.4kb|CCA_MODE=always,CHANBW_E=3,CHANSPC_E=0,DEVIATION_E=3,DEVIATION_M=4,DRATE_E=10,DRATE_M=131,FEC_EN=1,FREQ_IF=6,FSCAL=2836004881,MAX_DVGA_GAIN=not-top,MOD_FORMAT=GFSK,PA_POWER=7,RXOFF_MODE=RX,SYNC_MODE=30/32
MSK-250kb|AGC_LNA_PRIORITY=lna-first,BS_PRE_KI=KI,BS_PRE_KP=2KP,CCA_MODE=always,CHANBW_E=0,CHANBW_M=2,CHANSPC_E=0,DEVIATION_E=0,DEVIATION_M=0,DRATE_E=13,DRATE_M=59,FEC_EN=1,FILTER_LENGTH=32sa,FOC_LIMIT=BW/8,FOC_PRE_K=4K,FREQ_IF=11,FSCAL=3926523921,LN...
MSK-500kb|BS_PRE_KI=KI,BS_PRE_KP=2KP,CCA_MODE=always,CHANBW_E=0,CHANSPC_E=0,DEVIATION_E=0,DEVIATION_M=0,DRATE_E=14,DRATE_M=59,FEC_EN=1,FILTER_LENGTH=32sa,FOC_LIMIT=BW/8,FOC_PRE_K=4K,FREQ_IF=12,FSCAL=3926523929,LNA2MIX_CURRENT=3,LNA_CURRENT=2,MAGN_TAR...