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	.arch armv8.2-a+crypto+sha3
	.text
	.align	2
	.p2align 3,,7

/*
Macros
*/

.macro	declare_var_vector_reg name:req,reg:req
	\name\()_q	.req	q\reg
	\name\()_v	.req	v\reg
	\name\()_s	.req	s\reg
.endm
/**
maros for round 0-63
*/
.macro sha512_rounds_low ab,cd,ef,gh,tmp,msg0,msg1,msg4,msg5,msg7
	ldr		key_q , [key_adr]
	add		l0_tmp0_v.2d,l0_\msg0\()_v.2d,key_v.2d
	add		l1_tmp0_v.2d,l1_\msg0\()_v.2d,key_v.2d
	add		key_adr,key_adr,16


	ext		l0_tmp1_v.16b,l0_\ef\()_v.16b,l0_\gh\()_v.16b,#8
	ext		l1_tmp1_v.16b,l1_\ef\()_v.16b,l1_\gh\()_v.16b,#8


	ext		l0_tmp0_v.16b,l0_tmp0_v.16b,l0_tmp0_v.16b,#8
	ext		l1_tmp0_v.16b,l1_tmp0_v.16b,l1_tmp0_v.16b,#8


	ext		l0_tmp2_v.16b,l0_\cd\()_v.16b,l0_\ef\()_v.16b,#8
	ext		l1_tmp2_v.16b,l1_\cd\()_v.16b,l1_\ef\()_v.16b,#8


	add		l0_\gh\()_v.2d,l0_\gh\()_v.2d,l0_tmp0_v.2d
	add		l1_\gh\()_v.2d,l1_\gh\()_v.2d,l1_tmp0_v.2d


	ext		l0_tmp0_v.16b,l0_\msg4\()_v.16b,l0_\msg5\()_v.16b,#8
	ext		l1_tmp0_v.16b,l1_\msg4\()_v.16b,l1_\msg5\()_v.16b,#8

	sha512su0	l0_\msg0\()_v.2d,l0_\msg1\()_v.2d
	sha512su0	l1_\msg0\()_v.2d,l1_\msg1\()_v.2d

	sha512h		l0_\gh\()_q,l0_tmp1_q,l0_tmp2_v.2d
	sha512h		l1_\gh\()_q,l1_tmp1_q,l1_tmp2_v.2d

	sha512su1	l0_\msg0\()_v.2d,l0_\msg7\()_v.2d,l0_tmp0_v.2d
	sha512su1	l1_\msg0\()_v.2d,l1_\msg7\()_v.2d,l1_tmp0_v.2d

	add		l0_\tmp\()_v.2d,l0_\cd\()_v.2d,l0_\gh\()_v.2d
	add		l1_\tmp\()_v.2d,l1_\cd\()_v.2d,l1_\gh\()_v.2d

	sha512h2	l0_\gh\()_q,l0_\cd\()_q,l0_\ab\()_v.2d
	sha512h2	l1_\gh\()_q,l1_\cd\()_q,l1_\ab\()_v.2d
.endm

/**
maros for round 64-79
*/
.macro sha512_rounds_high	ab,cd,ef,gh,tmp,msg0
	ldr		key_q , [key_adr]
	add		l0_tmp0_v.2d,l0_\msg0\()_v.2d,key_v.2d
	add		l1_tmp0_v.2d,l1_\msg0\()_v.2d,key_v.2d
	add		key_adr,key_adr,16