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	.arch armv8-a+crypto
	.text
	.align	2
	.p2align 3,,7

/*
Macros
*/

.macro	declare_var_vector_reg name:req,reg:req
	\name\()_q	.req	q\reg
	\name\()_v	.req	v\reg
	\name\()_s	.req	s\reg
.endm
/**
maros for round 48-63
tmp0 : in
tmp1 : out
*/
.macro sha256_4_rounds_high msg:req,tmp0:req
	ldr		key_q , [tmp]
	mov		tmp0_v.16b,l0_\tmp0\()_v.16b
	mov		tmp1_v.16b,l1_\tmp0\()_v.16b
	add		l0_\tmp0\()_v.4s,l0_\msg\()_v.4s,key_v.4s
	add		l1_\tmp0\()_v.4s,l1_\msg\()_v.4s,key_v.4s
	mov		tmp2_v.16b,l0_abcd_v.16b
	mov		tmp3_v.16b,l1_abcd_v.16b
	sha256h		l0_abcd_q,l0_efgh_q,tmp0_v.4s
	sha256h		l1_abcd_q,l1_efgh_q,tmp1_v.4s
	sha256h2	l0_efgh_q,tmp2_q,tmp0_v.4s
	sha256h2	l1_efgh_q,tmp3_q,tmp1_v.4s

	ldr		key_q , [tmp]
	mov		tmp0_v.16b,l2_\tmp0\()_v.16b
	mov		tmp1_v.16b,l3_\tmp0\()_v.16b
	add		tmp,tmp,16
	add		l2_\tmp0\()_v.4s,l2_\msg\()_v.4s,key_v.4s
	add		l3_\tmp0\()_v.4s,l3_\msg\()_v.4s,key_v.4s
	mov		tmp2_v.16b,l2_abcd_v.16b
	mov		tmp3_v.16b,l3_abcd_v.16b
	sha256h		l2_abcd_q,l2_efgh_q,tmp0_v.4s
	sha256h		l3_abcd_q,l3_efgh_q,tmp1_v.4s
	sha256h2	l2_efgh_q,tmp2_q,tmp0_v.4s
	sha256h2	l3_efgh_q,tmp3_q,tmp1_v.4s


.endm
/**
maros for round 0-47
*/
.macro sha256_4_rounds_low msg0:req,msg1:req,msg2:req,msg3:req,tmp0:req
	sha256su0		l0_\msg0\()_v.4s,l0_\msg1\()_v.4s
	sha256su0		l1_\msg0\()_v.4s,l1_\msg1\()_v.4s
	sha256su0		l2_\msg0\()_v.4s,l2_\msg1\()_v.4s
	sha256su0		l3_\msg0\()_v.4s,l3_\msg1\()_v.4s
	sha256_4_rounds_high	\msg1,\tmp0
	sha256su1		l0_\msg0\()_v.4s,l0_\msg2\()_v.4s,l0_\msg3\()_v.4s
	sha256su1		l1_\msg0\()_v.4s,l1_\msg2\()_v.4s,l1_\msg3\()_v.4s
	sha256su1		l2_\msg0\()_v.4s,l2_\msg2\()_v.4s,l2_\msg3\()_v.4s
	sha256su1		l3_\msg0\()_v.4s,l3_\msg2\()_v.4s,l3_\msg3\()_v.4s
.endm


/*
Variable list
*/