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/**********************************************************************
  Copyright(c) 2019 Arm Corporation All rights reserved.

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  modification, are permitted provided that the following conditions
  are met:
    * Redistributions of source code must retain the above copyright
      notice, this list of conditions and the following disclaimer.
    * Redistributions in binary form must reproduce the above copyright
      notice, this list of conditions and the following disclaimer in
      the documentation and/or other materials provided with the
      distribution.
    * Neither the name of Arm Corporation nor the names of its
      contributors may be used to endorse or promote products derived
      from this software without specific prior written permission.

  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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	.arch armv8-a+crypto
	.text
	.align	2
	.p2align 3,,7

/*
Macros
*/

.macro	declare_var_vector_reg name:req,reg:req
	\name\()_q	.req	q\reg
	\name\()_v	.req	v\reg
	\name\()_s	.req	s\reg
.endm

/**
maros for round 4-67
*/
.macro sha1_4_rounds inst:req,msg0:req,msg1:req,msg2:req,msg3:req,abcd:req,e0:req,tmp0:req,e1:req,tmp1:req,k:req
	sha1h	l0_\e0\()_s, l0_\abcd\()_s
	sha1h	l1_\e0\()_s, l1_\abcd\()_s

	\inst	l0_\abcd\()_q,l0_\e1\()_s,l0_\tmp1\()_v.4s
	\inst	l1_\abcd\()_q,l1_\e1\()_s,l1_\tmp1\()_v.4s

	add 	l0_\tmp1\()_v.4s,l0_\msg3\()_v.4s,\k\()_v.4s
	add 	l1_\tmp1\()_v.4s,l1_\msg3\()_v.4s,\k\()_v.4s

	sha1su1	l0_\msg0\()_v.4s,l0_\msg3\()_v.4s
	sha1su1	l1_\msg0\()_v.4s,l1_\msg3\()_v.4s

	sha1su0	l0_\msg1\()_v.4s,l0_\msg2\()_v.4s,l0_\msg3\()_v.4s
	sha1su0	l1_\msg1\()_v.4s,l1_\msg2\()_v.4s,l1_\msg3\()_v.4s
.endm


/*
Variable list
*/

	declare_var_vector_reg	key_0,28
	declare_var_vector_reg	key_1,29
	declare_var_vector_reg	key_2,30
	declare_var_vector_reg	key_3,31


/*
lane variables
*/
	declare_var_vector_reg	l0_abcd,0
	declare_var_vector_reg	l0_e0,1
	declare_var_vector_reg	l0_e1,2
	declare_var_vector_reg	l0_abcd_saved,3
	declare_var_vector_reg	l0_e0_saved,4
	declare_var_vector_reg	l0_tmp_0,5
	declare_var_vector_reg	l0_tmp_1,6
	declare_var_vector_reg	l0_msg_0,16
	declare_var_vector_reg	l0_msg_1,17
	declare_var_vector_reg	l0_msg_2,18
	declare_var_vector_reg	l0_msg_3,19

	declare_var_vector_reg	l1_abcd,7
	declare_var_vector_reg	l1_e0,8
	declare_var_vector_reg	l1_e1,9
	declare_var_vector_reg	l1_abcd_saved,24
	declare_var_vector_reg	l1_e0_saved,25
	declare_var_vector_reg	l1_tmp_0,26