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infix/src/arch/riscv/abi_riscv64_emitters.h  view on Meta::CPAN

INFIX_INTERNAL void infix_riscv64_emit_sd(code_buffer * buf, uint8_t rs1, uint8_t rs2, int32_t imm12);
/**
 * @internal
 * @brief Emit a `sw rs2, imm12(rs1)` instruction (a 32-bit integer store).
 */
INFIX_INTERNAL void infix_riscv64_emit_sw(code_buffer * buf, uint8_t rs1, uint8_t rs2, int32_t imm12);
/**
 * @internal
 * @brief Emit a `fld rd, imm12(rs1)` instruction (a 64-bit FP load).
 */
INFIX_INTERNAL void infix_riscv64_emit_fld(code_buffer * buf, uint8_t rd, uint8_t rs1, int32_t imm12);
/**
 * @internal
 * @brief Emit a `fsd rs2, imm12(rs1)` instruction (a 64-bit FP store).
 */
INFIX_INTERNAL void infix_riscv64_emit_fsd(code_buffer * buf, uint8_t rs1, uint8_t rs2, int32_t imm12);
/**
 * @internal
 * @brief Emit a `flw rd, imm12(rs1)` instruction (a 32-bit FP load).
 */
INFIX_INTERNAL void infix_riscv64_emit_flw(code_buffer * buf, uint8_t rd, uint8_t rs1, int32_t imm12);
/**
 * @internal
 * @brief Emit a `fsw rs2, imm12(rs1)` instruction (a 32-bit FP store).
 */
INFIX_INTERNAL void infix_riscv64_emit_fsw(code_buffer * buf, uint8_t rs1, uint8_t rs2, int32_t imm12);
/**
 * @internal
 * @brief Emit a `fmv.d rd(FP), rs1(FP)` instruction (a 64-bit FP register move).
 */
INFIX_INTERNAL void infix_riscv64_emit_fmv_d(code_buffer * buf, uint8_t rd, uint8_t rs1);
/**
 * @internal
 * @brief Emit a `fmv.s rd(FP), rs1(FP)` instruction (a 32-bit FP register move).
 */
INFIX_INTERNAL void infix_riscv64_emit_fmv_s(code_buffer * buf, uint8_t rd, uint8_t rs1);
/**
 * @internal
 * @brief Emit a `fmv.w.x rd(FP), rs1(GPR)` instruction (copies the low 32 bits of a GPR
 *        into a 32-bit FP register).
 */
INFIX_INTERNAL void infix_riscv64_emit_fmv_w_x(code_buffer * buf, uint8_t rd, uint8_t rs1);
/**
 * @internal
 * @brief Emit a `fmv.x.w rd(GPR), rs1(FP)` instruction (copies the bits of a 32-bit FP
 *        register into a GPR).
 */
INFIX_INTERNAL void infix_riscv64_emit_fmv_x_w(code_buffer * buf, uint8_t rd, uint8_t rs1);
/**
 * @internal
 * @brief Emit a `fcvt.d.s rd(FP), rs1(FP)` instruction (widens a 32-bit float to 64-bit double).
 */
INFIX_INTERNAL void infix_riscv64_emit_fcvt_d_s(code_buffer * buf, uint8_t rd, uint8_t rs1);
/**
 * @internal
 * @brief Emit a `fcvt.s.d rd(FP), rs1(FP)` instruction (narrows a 64-bit double to 32-bit float).
 */
INFIX_INTERNAL void infix_riscv64_emit_fcvt_s_d(code_buffer * buf, uint8_t rd, uint8_t rs1);
/**
 * @internal
 * @brief Emit an `ebreak` instruction (a debugging trap).
 */
INFIX_INTERNAL void infix_riscv64_emit_ebreak(code_buffer * buf);
/**
 * @internal
 * @brief Load a signed 64-bit immediate value into a register using the standard `li`
 *        expansion. This mirrors how the AArch64 backend materializes large constants
 *        (e.g., for the reverse dispatcher or absolute function addresses).
 */
INFIX_INTERNAL void infix_riscv64_emit_load_u64_immediate(code_buffer * buf, uint8_t rd, uint64_t imm);