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#pragma once
/**
 * Copyright (c) 2026 Sanko Robinson
 *
 * This source code is dual-licensed under the Artistic License 2.0 or the MIT License.
 * You may choose to use this code under the terms of either license.
 *
 * SPDX-License-Identifier: (Artistic-2.0 OR MIT)
 *
 * The documentation blocks within this file are licensed under the
 * Creative Commons Attribution 4.0 International License (CC BY 4.0).
 *
 * SPDX-License-Identifier: CC-BY-4.0
 */
/**
 * @file abi_riscv64_common.h
 * @brief Common register definitions and instruction encodings for the RISC-V RV64GC architecture.
 * @ingroup internal_abi_riscv64
 *
 * @internal
 * This header serves two primary purposes for the RISC-V backend:
 *
 * 1.  **Register Enumerations:** It defines enums for the general-purpose registers (GPRs) and
 *     the floating-point registers (FPRs). These enums provide a clear, type-safe,
 *     and self-documenting way to refer to specific registers when emitting machine
 *     code or implementing the ABI logic. The comments on each register describe its
 *     role according to the standard RISC-V ELF psABI calling convention (lp64d).
 *
 * 2.  **Instruction Encoding Constants:** It contains preprocessor definitions for the
 *     fixed bitfields of various RISC-V instructions. This abstracts away the
 *     "magic numbers" of machine code generation, making the emitter code in
 *     `abi_riscv64_emitters.c` more readable and easier to verify against the
 *     RISC-V specification (Volume I: Unprivileged ISA).
 * @endinternal
 */
#include <stdint.h>
/**
 * @internal
 * @enum riscv_gpr
 * @brief Enumerates the RISC-V 64-bit General-Purpose Registers (x0-x31).
 *
 * @details The enum values (0-31) correspond directly to the 5-bit register numbers
 * used in the encoding of machine code instructions. The comments on each register
 * describe its primary role according to the RISC-V psABI.
 */
typedef enum {
    X_ZERO_REG = 0,  ///< x0: Hardwired zero. Reads return 0, writes are ignored.
    X_RA_REG,        ///< x1: Return Address. Set by `jal`/`jalr`; the standard link register.
    X_SP_REG,        ///< x2: Stack Pointer. Must always be 16-byte aligned.
    X_GP_REG,        ///< x3: Global Pointer (reserved for the ABI).
    X_TP_REG,        ///< x4: Thread Pointer (reserved for the ABI).
    X_T0_REG,        ///< x5: Temporary / caller-saved.
    X_T1_REG,        ///< x6: Temporary / caller-saved.
    X_T2_REG,        ///< x7: Temporary / caller-saved.
    X_S0_REG,        ///< x8: Saved register / Frame Pointer (`fp`). Callee-saved.
    X_S1_REG,        ///< x9: Saved register. Callee-saved.
    X_A0_REG = 10,   ///< x10: Argument 1 / Return value / caller-saved.
    X_A1_REG,        ///< x11: Argument 2 / Return value / caller-saved.
    X_A2_REG,        ///< x12: Argument 3 / caller-saved... (volatile).
    X_A3_REG,        ///< x13: Argument 4.
    X_A4_REG,        ///< x14: Argument 5.
    X_A5_REG,        ///< x15: Argument 6.
    X_A6_REG,        ///< x16: Argument 7.
    X_A7_REG,        ///< x17: Argument 8.
    X_S2_REG = 18,   ///< x18: Saved register. Callee-saved.
    X_S3_REG,        ///< x19: Saved register. Callee-saved.
    X_S4_REG,        ///< x20: Saved register. Callee-saved.
    X_S5_REG,        ///< x21: Saved register. Callee-saved.
    X_S6_REG,        ///< x22: Saved register. Callee-saved.
    X_S7_REG,        ///< x23: Saved register. Callee-saved.
    X_S8_REG,        ///< x24: Saved register. Callee-saved.
    X_S9_REG,        ///< x25: Saved register. Callee-saved.
    X_S10_REG,       ///< x26: Saved register. Callee-saved.
    X_S11_REG,       ///< x27: Saved register. Callee-saved.
    X_T3_REG = 28,   ///< x28: Temporary / caller-saved.
    X_T4_REG,        ///< x29: Temporary / caller-saved.
    X_T5_REG,        ///< x30: Temporary / caller-saved.
    X_T6_REG         ///< x31: Temporary / caller-saved.
} riscv_gpr;
/**
 * @internal
 * @enum riscv_fpr
 * @brief Enumerates the RISC-V 64-bit Floating-Point Registers (f0-f31).
 *
 * @details The enum values (0-31) correspond directly to the 5-bit register numbers
 * used in the encoding of FP instructions. In the LP64D psABI the floating-point