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#pragma once
/**
 * Copyright (c) 2025 Sanko Robinson
 *
 * This source code is dual-licensed under the Artistic License 2.0 or the MIT License.
 * You may choose to use this code under the terms of either license.
 *
 * SPDX-License-Identifier: (Artistic-2.0 OR MIT)
 *
 * The documentation blocks within this file are licensed under the
 * Creative Commons Attribution 4.0 International License (CC BY 4.0).
 *
 * SPDX-License-Identifier: CC-BY-4.0
 */
/**
 * @file abi_arm64_common.h
 * @brief Common register definitions and instruction encodings for the AArch64 (ARM64) architecture.
 * @ingroup internal_abi_aarch64
 *
 * @internal
 * This header serves two primary purposes for the AArch64 backend:
 *
 * 1.  **Register Enumerations:** It defines enums for the general-purpose registers (GPRs) and
 *     the floating-point/SIMD registers (VPRs). These enums provide a clear, type-safe,
 *     and self-documenting way to refer to specific registers when emitting machine
 *     code or implementing the ABI logic. The comments on each register describe its
 *     role according to the standard AAPCS64 calling convention.
 *
 * 2.  **Instruction Encoding Constants:** It contains preprocessor definitions for the
 *     fixed bitfields of various AArch64 instructions. This abstracts away the
 *     "magic numbers" of machine code generation, making the emitter code in
 *     `abi_arm64_emitters.c` more readable and easier to verify against the official
 *     ARM Architecture Reference Manual.
 *
 * By centralizing these definitions, this header provides a single source of truth for
 * the low-level architectural details, separating them from the higher-level ABI logic.
 * @endinternal
 */
#include <stdint.h>
/**
 * @internal
 * @enum arm64_gpr
 * @brief Enumerates the ARM64 General-Purpose Registers (GPRs), X0-X30 and SP.
 *
 * @details The enum values (0-31) correspond directly to the 5-bit register numbers
 * used in the encoding of machine code instructions. The comments on each register
 * describe its primary role according to the standard "Procedure Call Standard for
 * the ARM 64-bit Architecture" (AAPCS64), indicating whether it is used for
 * arguments, return values, or must be preserved across function calls (callee-saved).
 */
typedef enum {
    X0_REG = 0,   ///< Argument 1 / Return value / Volatile (caller-saved).
    X1_REG,       ///< Argument 2 / Volatile.
    X2_REG,       ///< Argument 3 / Volatile.
    X3_REG,       ///< Argument 4 / Volatile.
    X4_REG,       ///< Argument 5 / Volatile.
    X5_REG,       ///< Argument 6 / Volatile.
    X6_REG,       ///< Argument 7 / Volatile.
    X7_REG,       ///< Argument 8 / Volatile.
    X8_REG,       ///< Indirect Result Location Register (holds address for large struct returns) / Volatile.
    X9_REG,       ///< Volatile (caller-saved) scratch register.
    X10_REG,      ///< Volatile scratch register.
    X11_REG,      ///< Volatile scratch register.
    X12_REG,      ///< Volatile scratch register.
    X13_REG,      ///< Volatile scratch register.
    X14_REG,      ///< Volatile scratch register.
    X15_REG,      ///< Volatile scratch register.
    X16_REG,      ///< Intra-Procedure-call scratch register (IP0) / Volatile. May be modified by the linker.
    X17_REG,      ///< Intra-Procedure-call scratch register (IP1) / Volatile. May be modified by the linker.
    X18_REG,      ///< Platform Register (reserved, usage is platform-specific) / May be callee-saved. Best to avoid.
    X19_REG,      ///< Callee-saved. Must be preserved by a called function.
    X20_REG,      ///< Callee-saved.
    X21_REG,      ///< Callee-saved.
    X22_REG,      ///< Callee-saved.
    X23_REG,      ///< Callee-saved.
    X24_REG,      ///< Callee-saved.
    X25_REG,      ///< Callee-saved.
    X26_REG,      ///< Callee-saved.
    X27_REG,      ///< Callee-saved.
    X28_REG,      ///< Callee-saved.
    X29_FP_REG,   ///< Frame Pointer (FP) / Callee-saved.
    X30_LR_REG,   ///< Link Register (LR), holds the return address / Volatile across calls.
    SP_REG = 31,  ///< Stack Pointer (SP). In some instructions, encoding 31 refers to the Zero Register (XZR/WZR).
} arm64_gpr;
/**
 * @internal
 * @enum arm64_vpr
 * @brief Enumerates the ARM64 Floating-Point/SIMD (NEON) registers (V-registers).
 *