view release on metacpan or  search on metacpan

ffi/target/release/build/mlua-sys-6a99a2ae50f12319/out/luajit-build/build/src/vm_mips64.dasc  view on Meta::CPAN

|   .FPU sdc1 f30, SAVE_FPR_+6*8(sp)
|  sd r22, SAVE_GPR_+6*8(sp)
|   .FPU sdc1 f29, SAVE_FPR_+5*8(sp)
|  sd r21, SAVE_GPR_+5*8(sp)
|   .FPU sdc1 f28, SAVE_FPR_+4*8(sp)
|  sd r20, SAVE_GPR_+4*8(sp)
|   .FPU sdc1 f27, SAVE_FPR_+3*8(sp)
|  sd r19, SAVE_GPR_+3*8(sp)
|   .FPU sdc1 f26, SAVE_FPR_+2*8(sp)
|  sd r18, SAVE_GPR_+2*8(sp)
|   .FPU sdc1 f25, SAVE_FPR_+1*8(sp)
|  sd r17, SAVE_GPR_+1*8(sp)
|   .FPU sdc1 f24, SAVE_FPR_+0*8(sp)
|  sd r16, SAVE_GPR_+0*8(sp)
|.endmacro
|
|.macro restoreregs_ret
|  ld ra, SAVE_GPR_+9*8(sp)
|  ld r30, SAVE_GPR_+8*8(sp)
|  ld r23, SAVE_GPR_+7*8(sp)
|   .FPU ldc1 f31, SAVE_FPR_+7*8(sp)
|  ld r22, SAVE_GPR_+6*8(sp)
|   .FPU ldc1 f30, SAVE_FPR_+6*8(sp)
|  ld r21, SAVE_GPR_+5*8(sp)
|   .FPU ldc1 f29, SAVE_FPR_+5*8(sp)
|  ld r20, SAVE_GPR_+4*8(sp)
|   .FPU ldc1 f28, SAVE_FPR_+4*8(sp)
|  ld r19, SAVE_GPR_+3*8(sp)
|   .FPU ldc1 f27, SAVE_FPR_+3*8(sp)
|  ld r18, SAVE_GPR_+2*8(sp)
|   .FPU ldc1 f26, SAVE_FPR_+2*8(sp)
|  ld r17, SAVE_GPR_+1*8(sp)
|   .FPU ldc1 f25, SAVE_FPR_+1*8(sp)
|  ld r16, SAVE_GPR_+0*8(sp)
|   .FPU ldc1 f24, SAVE_FPR_+0*8(sp)
|  jr ra
|  daddiu sp, sp, CFRAME_SPACE
|.endmacro
|
|// Type definitions. Some of these are only used for documentation.
|.type L,		lua_State,	LREG
|.type GL,		global_State
|.type TVALUE,		TValue
|.type GCOBJ,		GCobj
|.type STR,		GCstr
|.type TAB,		GCtab
|.type LFUNC,		GCfuncL
|.type CFUNC,		GCfuncC
|.type PROTO,		GCproto
|.type UPVAL,		GCupval
|.type NODE,		Node
|.type NARGS8,		int
|.type TRACE,		GCtrace
|.type SBUF,		SBuf
|
|//-----------------------------------------------------------------------
|
|// Trap for not-yet-implemented parts.
|.macro NYI; .long 0xec1cf0f0; .endmacro
|
|// Macros to mark delay slots.
|.macro ., a; a; .endmacro
|.macro ., a,b; a,b; .endmacro
|.macro ., a,b,c; a,b,c; .endmacro
|.macro ., a,b,c,d; a,b,c,d; .endmacro
|
|.define FRAME_PC,	-8
|.define FRAME_FUNC,	-16
|
|//-----------------------------------------------------------------------
|
|// Endian-specific defines.
|.if ENDIAN_LE
|.define HI,		4
|.define LO,		0
|.define OFS_RD,	2
|.define OFS_RA,	1
|.define OFS_OP,	0
|.else
|.define HI,		0
|.define LO,		4
|.define OFS_RD,	0
|.define OFS_RA,	2
|.define OFS_OP,	3
|.endif
|
|// Instruction decode.
|.macro decode_OP1, dst, ins; andi dst, ins, 0xff; .endmacro
|.macro decode_OP8a, dst, ins; andi dst, ins, 0xff; .endmacro
|.macro decode_OP8b, dst; sll dst, dst, 3; .endmacro
|.macro decode_RC8a, dst, ins; srl dst, ins, 13; .endmacro
|.macro decode_RC8b, dst; andi dst, dst, 0x7f8; .endmacro
|.macro decode_RD4b, dst; sll dst, dst, 2; .endmacro
|.macro decode_RA8a, dst, ins; srl dst, ins, 5; .endmacro
|.macro decode_RA8b, dst; andi dst, dst, 0x7f8; .endmacro
|.macro decode_RB8a, dst, ins; srl dst, ins, 21; .endmacro
|.macro decode_RB8b, dst; andi dst, dst, 0x7f8; .endmacro
|.macro decode_RD8a, dst, ins; srl dst, ins, 16; .endmacro
|.macro decode_RD8b, dst; sll dst, dst, 3; .endmacro
|.macro decode_RDtoRC8, dst, src; andi dst, src, 0x7f8; .endmacro
|
|// Instruction fetch.
|.macro ins_NEXT1
|  lw INS, 0(PC)
|   daddiu PC, PC, 4
|.endmacro
|// Instruction decode+dispatch.
|.macro ins_NEXT2
|  decode_OP8a TMP1, INS
|  decode_OP8b TMP1
|  daddu TMP0, DISPATCH, TMP1
|   decode_RD8a RD, INS
|  ld AT, 0(TMP0)
|   decode_RA8a RA, INS
|   decode_RD8b RD
|  jr AT
|   decode_RA8b RA
|.endmacro
|.macro ins_NEXT
|  ins_NEXT1
|  ins_NEXT2

ffi/target/release/build/mlua-sys-6a99a2ae50f12319/out/luajit-build/build/src/vm_mips64.dasc  view on Meta::CPAN

|
|// Assumes DISPATCH is relative to GL.
#define DISPATCH_GL(field)	(GG_DISP2G + (int)offsetof(global_State, field))
#define DISPATCH_J(field)	(GG_DISP2J + (int)offsetof(jit_State, field))
#define GG_DISP2GOT		(GG_OFS(got) - GG_OFS(dispatch))
#define DISPATCH_GOT(name)	(GG_DISP2GOT + sizeof(void*)*LJ_GOT_##name)
|
#define PC2PROTO(field)  ((int)offsetof(GCproto, field)-(int)sizeof(GCproto))
|
|.macro load_got, func
|  ld CFUNCADDR, DISPATCH_GOT(func)(DISPATCH)
|.endmacro
|// Much faster. Sadly, there's no easy way to force the required code layout.
|// .macro call_intern, func; bal extern func; .endmacro
|.macro call_intern, func; jalr CFUNCADDR; .endmacro
|.macro call_extern; jalr CFUNCADDR; .endmacro
|.macro jmp_extern; jr CFUNCADDR; .endmacro
|
|.macro hotcheck, delta, target
|  dsrl TMP1, PC, 1
|  andi TMP1, TMP1, 126
|  daddu TMP1, TMP1, DISPATCH
|  lhu TMP2, GG_DISP2HOT(TMP1)
|  addiu TMP2, TMP2, -delta
|  bltz TMP2, target
|.  sh TMP2, GG_DISP2HOT(TMP1)
|.endmacro
|
|.macro hotloop
|  hotcheck HOTCOUNT_LOOP, ->vm_hotloop
|.endmacro
|
|.macro hotcall
|  hotcheck HOTCOUNT_CALL, ->vm_hotcall
|.endmacro
|
|// Set current VM state. Uses TMP0.
|.macro li_vmstate, st; li TMP0, ~LJ_VMST_..st; .endmacro
|.macro st_vmstate; sw TMP0, DISPATCH_GL(vmstate)(DISPATCH); .endmacro
|
|// Move table write barrier back. Overwrites mark and tmp.
|.macro barrierback, tab, mark, tmp, target
|  ld tmp, DISPATCH_GL(gc.grayagain)(DISPATCH)
|   andi mark, mark, ~LJ_GC_BLACK & 255		// black2gray(tab)
|  sd tab, DISPATCH_GL(gc.grayagain)(DISPATCH)
|   sb mark, tab->marked
|  b target
|.  sd tmp, tab->gclist
|.endmacro
|
|// Clear type tag. Isolate lowest 14+32+1=47 bits of reg.
|.macro cleartp, reg; dextm reg, reg, 0, 14; .endmacro
|.macro cleartp, dst, reg; dextm dst, reg, 0, 14; .endmacro
|
|// Set type tag: Merge 17 type bits into bits [15+32=47, 31+32+1=64) of dst.
|.macro settp, dst, tp; dinsu dst, tp, 15, 31; .endmacro
|
|// Extract (negative) type tag.
|.macro gettp, dst, src; dsra dst, src, 47; .endmacro
|
|// Macros to check the TValue type and extract the GCobj. Branch on failure.
|.macro checktp, reg, tp, target
|  gettp AT, reg
|  daddiu AT, AT, tp
|  bnez AT, target
|.  cleartp reg
|.endmacro
|.macro checktp, dst, reg, tp, target
|  gettp AT, reg
|  daddiu AT, AT, tp
|  bnez AT, target
|.  cleartp dst, reg
|.endmacro
|.macro checkstr, reg, target; checktp reg, -LJ_TSTR, target; .endmacro
|.macro checktab, reg, target; checktp reg, -LJ_TTAB, target; .endmacro
|.macro checkfunc, reg, target; checktp reg, -LJ_TFUNC, target; .endmacro
|.macro checkint, reg, target	// Caveat: has delay slot!
|  gettp AT, reg
|  bne AT, TISNUM, target
|.endmacro
|.macro checknum, reg, target	// Caveat: has delay slot!
|  gettp AT, reg
|  sltiu AT, AT, LJ_TISNUM
|  beqz AT, target
|.endmacro
|
|.macro mov_false, reg
|  lu reg, 0x8000
|  dsll reg, reg, 32
|  not reg, reg
|.endmacro
|.macro mov_true, reg
|  li reg, 0x0001
|  dsll reg, reg, 48
|  not reg, reg
|.endmacro
|
|//-----------------------------------------------------------------------

/* Generate subroutines used by opcodes and other parts of the VM. */
/* The .code_sub section should be last to help static branch prediction. */
static void build_subroutines(BuildCtx *ctx)
{
  |.code_sub
  |
  |//-----------------------------------------------------------------------
  |//-- Return handling ----------------------------------------------------
  |//-----------------------------------------------------------------------
  |
  |->vm_returnp:
  |  // See vm_return. Also: TMP2 = previous base.
  |  andi AT, PC, FRAME_P
  |  beqz AT, ->cont_dispatch
  |
  |  // Return from pcall or xpcall fast func.
  |.  mov_true TMP1
  |  ld PC, FRAME_PC(TMP2)		// Fetch PC of previous frame.
  |  move BASE, TMP2			// Restore caller base.
  |  // Prepending may overwrite the pcall frame, so do it at the end.
  |   sd TMP1, -8(RA)			// Prepend true to results.
  |   daddiu RA, RA, -8