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ffi/target/release/build/mlua-sys-6a99a2ae50f12319/out/luajit-build/build/src/vm_mips.dasc  view on Meta::CPAN

|  sw ra, SAVE_GPR_+9*4(sp)
|  sw r30, SAVE_GPR_+8*4(sp)
|   .FPU sdc1 f30, SAVE_FPR_+5*8(sp)
|  sw r23, SAVE_GPR_+7*4(sp)
|  sw r22, SAVE_GPR_+6*4(sp)
|   .FPU sdc1 f28, SAVE_FPR_+4*8(sp)
|  sw r21, SAVE_GPR_+5*4(sp)
|  sw r20, SAVE_GPR_+4*4(sp)
|   .FPU sdc1 f26, SAVE_FPR_+3*8(sp)
|  sw r19, SAVE_GPR_+3*4(sp)
|  sw r18, SAVE_GPR_+2*4(sp)
|   .FPU sdc1 f24, SAVE_FPR_+2*8(sp)
|  sw r17, SAVE_GPR_+1*4(sp)
|  sw r16, SAVE_GPR_+0*4(sp)
|   .FPU sdc1 f22, SAVE_FPR_+1*8(sp)
|   .FPU sdc1 f20, SAVE_FPR_+0*8(sp)
|.endmacro
|
|.macro restoreregs_ret
|  lw ra, SAVE_GPR_+9*4(sp)
|  lw r30, SAVE_GPR_+8*4(sp)
|   .FPU ldc1 f30, SAVE_FPR_+5*8(sp)
|  lw r23, SAVE_GPR_+7*4(sp)
|  lw r22, SAVE_GPR_+6*4(sp)
|   .FPU ldc1 f28, SAVE_FPR_+4*8(sp)
|  lw r21, SAVE_GPR_+5*4(sp)
|  lw r20, SAVE_GPR_+4*4(sp)
|   .FPU ldc1 f26, SAVE_FPR_+3*8(sp)
|  lw r19, SAVE_GPR_+3*4(sp)
|  lw r18, SAVE_GPR_+2*4(sp)
|   .FPU ldc1 f24, SAVE_FPR_+2*8(sp)
|  lw r17, SAVE_GPR_+1*4(sp)
|  lw r16, SAVE_GPR_+0*4(sp)
|   .FPU ldc1 f22, SAVE_FPR_+1*8(sp)
|   .FPU ldc1 f20, SAVE_FPR_+0*8(sp)
|  jr ra
|  addiu sp, sp, CFRAME_SPACE
|.endmacro
|
|// Type definitions. Some of these are only used for documentation.
|.type L,		lua_State,	LREG
|.type GL,		global_State
|.type TVALUE,		TValue
|.type GCOBJ,		GCobj
|.type STR,		GCstr
|.type TAB,		GCtab
|.type LFUNC,		GCfuncL
|.type CFUNC,		GCfuncC
|.type PROTO,		GCproto
|.type UPVAL,		GCupval
|.type NODE,		Node
|.type NARGS8,		int
|.type TRACE,		GCtrace
|.type SBUF,		SBuf
|
|//-----------------------------------------------------------------------
|
|// Trap for not-yet-implemented parts.
|.macro NYI; .long 0xec1cf0f0; .endmacro
|
|// Macros to mark delay slots.
|.macro ., a; a; .endmacro
|.macro ., a,b; a,b; .endmacro
|.macro ., a,b,c; a,b,c; .endmacro
|
|//-----------------------------------------------------------------------
|
|// Endian-specific defines.
|.if ENDIAN_LE
|.define FRAME_PC,	-4
|.define FRAME_FUNC,	-8
|.define HI,		4
|.define LO,		0
|.define OFS_RD,	2
|.define OFS_RA,	1
|.define OFS_OP,	0
|.else
|.define FRAME_PC,	-8
|.define FRAME_FUNC,	-4
|.define HI,		0
|.define LO,		4
|.define OFS_RD,	0
|.define OFS_RA,	2
|.define OFS_OP,	3
|.endif
|
|// Instruction decode.
|.macro decode_OP1, dst, ins; andi dst, ins, 0xff; .endmacro
|.macro decode_OP4a, dst, ins; andi dst, ins, 0xff; .endmacro
|.macro decode_OP4b, dst; sll dst, dst, 2; .endmacro
|.macro decode_RC4a, dst, ins; srl dst, ins, 14; .endmacro
|.macro decode_RC4b, dst; andi dst, dst, 0x3fc; .endmacro
|.macro decode_RD4b, dst; sll dst, dst, 2; .endmacro
|.macro decode_RA8a, dst, ins; srl dst, ins, 5; .endmacro
|.macro decode_RA8b, dst; andi dst, dst, 0x7f8; .endmacro
|.macro decode_RB8a, dst, ins; srl dst, ins, 21; .endmacro
|.macro decode_RB8b, dst; andi dst, dst, 0x7f8; .endmacro
|.macro decode_RD8a, dst, ins; srl dst, ins, 16; .endmacro
|.macro decode_RD8b, dst; sll dst, dst, 3; .endmacro
|.macro decode_RDtoRC8, dst, src; andi dst, src, 0x7f8; .endmacro
|
|// Instruction fetch.
|.macro ins_NEXT1
|  lw INS, 0(PC)
|   addiu PC, PC, 4
|.endmacro
|// Instruction decode+dispatch.
|.macro ins_NEXT2
|  decode_OP4a TMP1, INS
|  decode_OP4b TMP1
|  addu TMP0, DISPATCH, TMP1
|   decode_RD8a RD, INS
|  lw AT, 0(TMP0)
|   decode_RA8a RA, INS
|   decode_RD8b RD
|  jr AT
|   decode_RA8b RA
|.endmacro
|.macro ins_NEXT
|  ins_NEXT1
|  ins_NEXT2